Soft Error Sensitivity Analysis And Reliability Optimization Techniques For Digital Integrated Circuits

Soft error is a phenomenon of the random storage data decaying of circuit nodes inducedby radiations. The protection of soft error is a must issue to be concerned for thehigh reliability devices used in the military and space environments. By the technologyadvancing of integrated circuits (ICs), soft error has been the main issue for the reliabilitydegradation of modern deep sub-micron ICs. For example, even the atmosphere neutronbackground radiation at sea level has enough energy to upset the modern nanometerCMOS digital ICs. Hence, the researching of soft error of digital ICs is significant intheory and reality for the development of the nation's ICs industry and the promotion ofindependent manufacturing level of defence equipments.The soft error sensitivity (soft error rate) characterization technique in design stageis the foundation of developing soft error tolerance high reliability digital ICs. With thesupports of soft error sensitivity characterization methods and tools, the reliability of thesystem can be analyzed on-demand in all the design stages. Hence, we can prevent theincompetent designs from entering into the next stage, decreasing the design iterations andsaving time and costs.This dissertation focused on the soft error sensitivity characterization and soft errortolerance optimization and hardening techniques of digital ICs in design stage, whichmainly includes the following works:Firstly, a unified theoretical model is constructed to direct the design of the simulatedfault injection systems. Based on the theoretical model, a simulated fault injectiontechnique is developed,which is designed for the VHDL and Verilog based designs andbe appropriate for the high level soft error sensitivity characterization. In the proposedplatform, VHDL and Verilog syntax analysis techniques are employed to parse the HDLcodes, extract the information of fault injection targets and build the fault injection scriptsautomatically; simulator commands based simulated fault injection technique is employedto inject bit-flip faults into the system; stratified sampling technique is used to decreasethe number of faults demanded to be injected, shorten the time consuming and minimizethe statistical variance of the soft error sensitivity evaluation; data mining technique isemployed to process the experiment results to analyze the relationship among the internal modules. Experiments carried out on the DP32 microprocessor show that the proposedtechnique can characterize the soft error sensitivity of register transfer level, system andbehavioral level models efficiently.Secondly, a simulated fault injection method based on circuit level simulation is developedand employed to characteristics the soft error sensitivity. The strike of the radiationparticle will generate a short glitch between the drain and bulk of the transistor that canbe modeled by a exponential current source. By using circuit level simulated fault injectiontechnique, the generation and propagation characteristics of the exponential currentsource can be characterized from the analog perspective with much higher accuracy. Thefast Spice simulator is used for the fault injection experiments in this thesis to overcomethe deficiency of lower speed of the traditional HSpice simulator. Spice syntax analysistechnique is employed to automate the fault injection experiment, flatten the Spicenetlist, extract fault injections targets and insert current sources representing the soft errorautomatically. Stratified sampling and check-point recovery techniques are employed todecrease the time consuming of the soft error sensitivity evaluation and promote the statisticalaccuracy. The proposed technique can also be used to inject faults into dynamiccircuits that hard to be model by logical simulation methods. By extracting parasiticalparameters from layouts and back annotating the RC delay data, the proposed techniqueeven can do reliability evaluation for post-layout circuits. The proposed technique hasspecial value and is superior in both characterization accuracy and applied circuit types.Thirdly, a fast soft error rate calculation method is proposed, which is based on theanalytical model and appropriate for the evaluation of combinational logic circuits. Thismethod targets on the standard cell circuit, which reads synthesized Verilog netlist as theinputs and calculates the soft error rate by studying the generating, propagating and maskingcharacteristics of the soft error glitches in the circuit. The evaluation speed of theproposed technique is superior than simulated fault injection techniques. By employingVerilog syntax analysis and syntax directed translation techniques, the proposed methodcan extract the combinational parts of sequential logic circuits and characterize only thesoft error rate of the combinational parts, which make our technique superior in the appliedcircuit types than the other analytical model based methods. There are two working modesin the proposed method: accuracy first mode and speed first mode. In accuracy first mode,similar characterization results are obtained compared to the other international research works; in speed first mode, the technique has lower accuracy but much higher speeds withthree magnitudes promotion and has special value in the fields demanding rapidly softerror sensitivity evaluation.Finally, by using the above speed first soft error rate characterization method, a softerror tolerance optimization scheme is proposed, which is based on the multi-objectivegenetic algorithm and can be used for the hardening of the combinational logic circuits.The optimization technique utilizing the fact that the logic gates in the standard cell librarywith identical function but different geometry sizes have distinct glitches generation andpropagation characteristics. It use multi-objective genetic algorithm to configure the sizesof logic gates in the Verilog netlist optimally to optimize the soft error tolerance ability ofthe circuit. The experiments show that the proposed method has better composite performancewith similar hardening effects but much lower area and delay cost compared to theother works.Soft error sensitivity characterization is the foundation and the difficulty of designingsoft error tolerance high reliability ICs. The soft error sensitivity characterization andoptimization techniques proposed in this dissertation can effectively direct the design ofhigh reliability ICs with better theoretical significance and practical applying values.