Dynamic threshold MOSFETs for future integrated circuits

As scaling of transistors continues to sub-tenth micron channel lengths, supply voltages must also be scaled in order to manage power dissipation. This will hinder circuit performance because lower supply voltages will cause transistors to have less current drive. The best way to keep some of the current lost due to lower supply voltage is to lower the threshold voltage, V_t, of the transistors. However, there is a limit to how much V_t can be lowered—if it is too low, it becomes impossible to turn the transistors off. Given this analysis, a tunable threshold voltage is highly desirable; the ability to increase V_t when the transistor is off to suppress leakage and to decrease V_t in the on-state to boost current drive is the key to maintaining circuit performance while keeping power dissipation under control.; This work focuses on methods to dynamically adjust the threshold voltage of a MOS transistor by using the body or backgate node of the device. Chapter 1 gives additional motivation and background to dynamic threshold MOS (DTMOS) transistors. It also reviews some of the previous work performed on this topic. Chapter 2 presents experimental results from DTMOS devices and compares them to conventional, fixed threshold devices. Chapter 3 sets up the theory for dynamic threshold voltage and shows how to optimize DTMOS performance. The asymmetric double gate MOSFET is proven to be the optimal DTMOS and is compared to the symmetric double gate in Chapter 4. Chapter 5 describes the FinFET, a quasi-planar structure which can implement both the asymmetric and symmetric double gate structures. Lastly, in order to investigate circuit performance for the FinFET, extensive 2D and 3D simulations were performed. The results are reported and analyzed in Chapter 6.