| Time-interleaving parallel channels can increase the maximum sampling rate of analog-to-digital converters (ADCs). However, the performance is degraded by offset mismatches, gain mismatches, and sample-time errors between the interleaved channels [1]. Digital calibration to overcome sample-time errors has been demonstrated but is limited to only two channels [2]. Double sampling can reduce the power dissipation and area [3], but sharing opamps across channels can introduce memory errors not previously overcome by calibration. This thesis describes a double-sampled pipelined ADC using digital calibration to overcome the effects of mismatch errors between four channels, as well as memory errors across channels introduced by double sampling.;To demonstrate the digital calibration approach, an 11b 160MS/s 4-channel time-interleaved double-sampled pipelined ADC has been designed and fabricated in a 0.35microm CMOS process. Digital calibration is used to correct mismatch errors between channels as well as memory errors that arise from the use of double sampling. With a 8.71-MHz input, test results show that the calibration improves the SNDR from 45 to 62dB and the SFDR from 47 dB to 78 dB. The total power dissipation is 594mW from a 3.3 V power supply. The active area is 13.9 mm2. |
