Research And Design Of 16 Bit Sigma-Delta Modulator With Double Sampling

Analog-to-digital converters have an indispensable position in this rapidly developing informational and digital world.Sigma-delta modulator is one of a widely recognized analog to digital converters that is especially suitable for high-resolution.By employing oversampling and quantization noise shaping technique,Sigma-delta modulator can achieve high signal-to-noise ratio with effective bandwidth that others analog-to-digital cannot do.And through making compromise between speed and accuracy,high accuracy can be obtained.The Sigma-delta modulator is usually used among low to medium speed analog-to-digital converters field,such as high-quality digital audio,motor drives,medical electronics,industrial motor driver and so on.Sigma-delta ADC is composed of Sigma-delta modulator and digital filter,and Sigma-delta modulator is studied in this paper.A one-bit quantized second-order single-loop cascade of integrators feed-forward topology(CIFF)is applied in the modulator.The low-frequency noise and the offset voltage are decreased by the chopper technology.Compared with the conventional fully-differential structure,the four sampling capacitances are used in each level of integrator.It means that the integrator achieves sample and integral twice a clock cycle.Therefore,the required external clock frequency of this integrator is only one half that of the traditional integrator's and the design requirements of the SR and GBW of the OPAMP are also reduced,which means that the design of the low power becomes true.The main work of this thesis includes: The second order CIFF structure as the circuit topology is selected according to the requirement of the system;the ideal model is established and the path coefficient of the system is identified;the operational amplifier parameter is calculated,the non-ideal factors in the circuit design is analyzed,such as the mismatch of capacitance,the switch and the amplifier,and the non-ideal model is built up to guide the circuit design;the circuit of the modulator with double-sampling structure is analyzed,simulated and optimized,the design and the post-simulation of the circuit is made,and the output of the bit stream of the post-simulation results of the entire circuit is analyzed through the Fast FourierTransform Algorithm,making the post-simulation results achieve the design specifications in all process corners.Based on the 0.35?m CMOS technique,and under the circumstances that the supply voltage is 5V,the sampling frequency is 10 MHz,and the oversampling rate is256,the simulation results show: the modulator achieves a distortion of signal-to-noise ratio of 99.3 dB,a total harmonic distortion of 104.7 dB,and an effective number of bit of 16.46.Most importantly,the total circuit power consumption is only 8 mW.