Digital Calibration Methods Research On Complexity And Power Reduction Of ADC In OFDM Receivers

OFDM technology is a kind of advanced physical layer multicarriermodulation technology, more and more digital, high speed and low powerwireless communication systems adopt OFDM technology as its keytechnology. OFDM based, high transmission rate of Gigabit/s, low powerwireless communication system become the new hot spot oncommunication research. This put forward high request on the existingelectronic devices, especially for implementation complexity and powerconsumption of the Analog to Digital Converter (ADC).The existing ADC is hard to keep the sampling resolution whileproviding sufficient high sampling rate. Time interleaved Analog to DigitalConverter (TIADC) is a kind of effective solutions. By multiple parallelsub-ADCs tuning the clock phase, the sampling rate of TIADC increaseswhile keep the resolution the same with the sub-ADCs. But the parametermismatch among sub-ADCs of the TIADC will greatly degrade the overallperformance of the system. This paper presents a calibration algorithm forDC offset mismatch of the TIADC. Based on OFDM comb pilots, thecalibration utilizes LMS and RLS adaptive filtering technology to solve themathematical model. The algorithm can calibrate two TIADCs in IQbranches at the same time. It also has the advantages of fast convergencespeed, and it does not need to generate additional training sequences. Inthis way, in the high speed OFDM receiver, a rough TIADC withoutcalibration can work normally. By doing this, the ADC implementation complexity has been effectively reduced.Further, in order to reduce ADC power consumption in OFDMreceivers, this paper put forward a timing synchronization algorithm basedon the symbol rate sampling, reducing the power consumption of the ADCby lowering the ADC sampling rate. By introducing the multiphase clock(a group of clocks that have the same frequency and are spacing by thesame phase) and the maximum absolute squared-sum (MASS) method tocontrol the ADC sampling time, the ADC sampling frequency is reduced tosymbol rate; Further, this paper puts forward a kind of adaptiveinterpolation filtering method, used to compensate for the residue clockerror caused by clock jitter, clock number shortage or other factors. Thesampling values are processed by an adaptive interpolator, and the tapcoefficients are updated by least mean square (LMS) algorithm.Simulationresults show that, the proposed timing recovery method can effectivelyreduce the influence of residual clock error. Thus, with the fuction of thenew method, the sampling rate reduces to the symbol rate, which meansthat the method can significantly reduce the power consumption of thewireless communication system.