The Digital Background Calibration Of Sampling Time Mismatch Error Based On TIADC

With the development of high speed communication system,the demand for higher speed and higher resolution ADCs become more and more urgent.Based on the CMOS technology and the design method of analog-to-digital conversion,the use of multi-channel time Interleaved technology to break the speed limit of single channel ADC has become an inevitable trend.The application of TIADC technology is proposed to achieve high speed and high precision ADC,but because of the high sampling rate,the minimum mismatch errors will result in a sharp drop in the accuracy of the TIADC system.Therefore,it is necessary to adopt a calibration algorithm to eliminate errors and improve the dynamic performance of the TIADC output signal.The basic principle of the TIADC system,the related performance parameters and the source of the errors are introduced.The TIADC error model is established basing on the existing research.This paper analyzes the influence of the offset mismatch error,the gain mismatch error and the sampling time mismatch error on the performance of the TIADC system,and summarizes the existing calibration methods for the sampling time mismatch error.The estimation algorithm of sampling time mismatch error based on Hilbert change is presented.The algorithm uses the input signal itself to estimate the error and does not introduce extra reference channels.By using MATLAB,the model of the error estimation algorithm is constructed.The simulation results show that the algorithm can accurately estimate the sampling time mismatch error.The all-digital background calibration algorithm based on differential FIR filter is proposed to calibrate the sampling time mismatch error of the TIADC system.By recombining M-channel TIADC's output date,M/2 2-channel TIADCs will be obtained.Then using the differential FIR filter and the estimated error to calibrate the new-formed TIADCs and repeat the process described above until the error is finally calibrated.By using this calibration algorithm,the error caused by the sampling time mismatch is greatly calibrated.A 4-channel TIADC with only sampling time mismatch error is used to simulate and verify the proposed algorithm.The simulation results demonstrate the effectiveness of the technique,in which the SFDR,the SNDR and the ENOB performance of the TIADC are improved from 60.2dB,56.3dB and 9.06bit to 81.0dB,94.5dB,13.2bit with the input frequency being 0.01f_s,respectively.After calibration,the SFDR and SNDR increased by more than 10dB in the whole Nyquist bandwidth.The key circuit of the error calibration algorithm is realized by Verilog language.The FIR filter adopts parallel structure,and the filter coefficients are quantized.By using TXT file,the joint simulation of MATLAB and Modelsim is carried out on the FIR filter circuit.The area,power consumption analysis and timing analysis of the circuit are completed basing on the SMIC 0.18?m 1.8V 1P6M standard CMOS technology library.Compared with the MATLAB,the SFDR,SNDR and the ENOB simulation results of Modelsim are reduced only by 3.2dB,2.9dB and 0.52bit.The results of the compiling shows that the FIR filter circuit has 548 cells,of which there are 356 combinational logic cells,and 192 sequential logic cells,with a total area of 33410.944628?m~2.The dynamic power is 20.4810mW,and the static power consumption of only 2.4718?W.