Laser Driver Design in 0.18 micron CMOS Technology

This thesis presents the design and analysis of two high speed analog laser driver stages (LDS) for use in a passive optical network (PON) upstream burst-mode transmitter (BM-Tx) using low cost complementary metal oxide semiconductors (CMOS) technology. The maturation of CMOS technology has lead to aggressive scaling of device sizes which has made it an increasingly attractive technology for high speed analog design. CMOS provides high levels of integration as it is the industry standard for digital circuits, analog and digital systems can share one substrate reducing costs. Additionally CMOS is a more cost effective solution than traditional expensive high speed analog substrates.;A 10 Gbps LDS fabricated in 0.18 mum CMOS technology is also presented. The LDS uses a cascode differential pair for the output stage. The pre-amplifier for this design consists of a differential pair and utilizes spiral inductors for series inductive peaking between the pre-amplifier and output stage. Measurements of S-parameters are presented which accurately agree with simulations. Electrical eye diagram measurements are presented which demonstrate the LDS is able to provide a modulation current of 22.6-62 mA. 10%-90% rise/fall time of 87 ps and 75 ps are respectively obtained while operating at maximum modulation current. The core of the LDS consumes a power of 287 mW, while the chip consumed an area of 0.79 x 0.7 mm2. Bias currents greater than 50 mA were obtained while performing DC testing.;The measured electrical eye diagrams for the 2.5 Gbps and the 10 Gbps meet the timing requirements for the GPON standard. Further work is needed to investigate whether or not the timing requirements would still be met once the CMOS chips are integrated with commercial laser diodes.;A 2.5 Gbps LDS fabricated in 0.18 mum CMOS technology is presented. The LDS uses a two stage pre-amplifier. Stage one consists of a cascode differential pair with a source follower voltage buffer, while stage two consists of a shunt inductively peaked differential pair using active inductors. A differential pair composed of large transistors is used in an open drain configuration for the output stage. Measurements of S-parameters are presented which accurately agree with simulations. Electrical eye diagram measurements are presented which demonstrate the LDS is able to provide a modulation current of 14.6-58 mA to a 50 O load. A 10%-90% approximate rise/fall time of 200 ps was obtained for modulation currents below 44 mA, while a rise/fall time of 230/260 ps was obtained for a modulation current of 58 mA. Power consumption of the core was determined to be 68.5 mW, while the chip consumed an area of 0.8 x 0.7 mm2 including pads. Bias currents greater than 50 mA were achieved under DC testing.