Linearization and applications of the CMOS Quad

A symmetrical differential pair can only generate an output current that is an odd function of the differential input voltage whereas, a pair with a deliberate mismatch introduced can create an output current that has both odd and even components. Such a pair is said to be a 'skewed pair'. The degree of mismatch can be controlled to vary the proportion of odd and even components in the output current. If we take two identical skewed pairs and transpose them with respect to each other and connect them in parallel, we obtain the 'Quad'. The CMOS Quad is built with four MOSFETs. The output currents generated by the skewed pairs can be combined to generate two useful output currents: one that is purely an odd function and the other, a purely even. The odd component turns out to be more linear than that of a symmetric differential pair. The even component derived happens to be a square-law output current. This even component generated in the Quad can be used to linearize a symmetrical differential pair.;Linearity of the CMOS Quad can be increased by selectively feeding back the even component of the output current to its bias current. This linearization technique does not need any resistors. As an application, a transconductor-capacitor based fourth order Butterworth filter is implemented using a low-noise analog 0.6 mum TI process with the linearized Quad as a transconductor. The measurement results are presented. Feasibility of this linearized Quad to implement 'precise gain amplifiers' is explored. These amplifiers can be used in buffer or pipeline converters. A variation of the CMOS Quad, known as 'series connected Quad' is introduced to increase input swing capability of the CMOS Quad. On-chip linear resistors can be implemented using a series connected Quad.;Using the linear and square-law current generated in the CMOS Quad, a novel structure for low-swing CMOS Latch is proposed. This latch can be used in high-speed comparators where kick-back is the main concern. True RMS detectors can be built using the even component generated in the CMOS Quad. With minimum area and power overhead, this differential block can be readily used for on-chip RF testing. A prototype of this RMS detector is fabricated in 0.18 mum TSMC process. The measurement results are presented. Design of four-quadrant multipliers using the CMOS Quad is discussed.;The key contribution of this dissertation is the self-linearization of the CMOS Quad by selective even feedback that also removes common-mode even component at the output of the CMOS Quad. Three applications of the CMOS Quad are presented. The proposed circuits in this dissertation do not use any resistors and they are particularly useful for the fabrication in low-voltage standard digital CMOS processes.