Research And Application Based On LDPC Decoding Algorithm

Low-Density Parity-Check code,as an important linear block code,has error correction performance close to Shannon's limit,and has been widely used in satellite communication and deep space communication.It is adopted by many industry standards such as WLAN,WiMAX and DVB-S2.Therefore,it is of practical significance to further study the LDPC application field and study the efficient decoder design.This article mainly includes the following three points:(1)LDPC-based information redundancy design.With the reduction of digital circuit reliability,it becomes more necessary to improve the fault tolerance of digital circuits,and traditional hardware redundancy will bring huge overhead in area and power consumption.In this paper,LDPC is used to realize information redundancy design,and hardware redundancy and information redundancy fault-tolerant structure are simulated and analyzed in the range of ? ?(7)0.0001,0.1(8).The results show that: when ?(27)0.05,the information redundancy is lower than the hardware redundancy Bit Error Rate.Conversely,the hardware redundancy BER is lower than the information redundancy.Further,the information redundancy is implemented on the Xilinx FPGA platform to give resource consumption.(2)In order to improve the efficiency of decoder design,this paper studies the automatic generation platform of CNFU for NMS decoding algorithm.The platform automatically generates a Verilog file corresponding to the CNFU through parameters such as the number of input variables,the correction factor,and the output path.In order to make the CNFU generated by the platform have better performance,various aspects such as correction factor,quantization precision,and TS structure are optimized.The platform can be applied to different standard LDPC codes,and has practical value for improving the design efficiency of the decoder.(3)Finally,the paper studies the design and implementation of high-efficiency LDPC decoder for WiMAX standard,and considers optimization from hierarchical decoding structure,memory form and pipeline design.And verified on the Xilinx XC7A100 TFPGA platform,the 240 Mbps throughput rate can be obtained and the performance only loses 0.1dB~0.2dB compared with the floating point number.The research content of this paper verifies that LDPC-based information redundancy faulttolerant design and efficient LDPC decoder design have engineering application value.