An ASIC Design Of A Kind Of LDPC Decoder

In recent years,wireless communication technology can be seen everywhere in people's lives.With the IOT,AI,big data and the like has becoming the main directions for the development of technology,wireless communications are increasingly challenged in terms of reliability.In order to reduce the noise interference received when the information is transmitted in the channel,channel coding is widely accepted.LDPC code is currently the mainstream channel coding solution.LDPC codes are low-density parity-check codes,it has excellent encoding performance.LDPC decoder is the key of this technology,it uses a series of calibration equations to perform a large number of iterations on the received data,eliminating the channel noise interference,in order to get the correct information.Due to its ‘low density' characteristics,it reduces the amount of data when calculating the calibration equation,and the iterative computation mechanism is very suitable for hardware implementation.However,there are still some shortcomings in the development of the LDPC decoder,such as the inability to balance the throughput and resource consumption,the excessive internal storage requirements,and so on.Moreover,flexibility has become an important feature,the receiving end always needs to decode information with different code rates or even different code lengths.In summary,the design of a new type of LDPC decoder is of great significance.In this paper,a new type of LDPC decoder based on BDS-CDRadio technology is designed based on the enterprise project.BDS-CDRadio technology,also known as ‘JIHE Beidou Navigation System' is a set of Beidou satellite high-precision navigation and positioning solution.Decoder architecture using part of the parallel architecture,to ensure that the decoding speed while reducing resource consumption.The algorithm chooses the TDMP decoding algorithm and calculates the posterior information by using the normalized minimum sum algorithm.In the storage of received codeword,a new storage scheme is proposed,which can output multiple codewords in the same clock cycle and reduce the decoding delay.In terms of the storage of the check matrix and the a posteriori information,a new optimization scheme is proposed to compress the originally tedious data and reduce the storage space requirement.While ensuring the performance,the decoder can simultaneously support four kinds of code rates as 2/3,1/2,1/3 and 1/4,and can be configured externally by the parity check matrix.Under the premise of ensuring the matrix specification,it can support any check matrix with a strong flexibility.The design was initially based on the FPGA platform and was later used in the enterprise ASIC project ‘JIHE SK9042',a mobile receiving chip for the BDS-CDRadio system that has been tape-out successfully.At 150 M frequency and assuming the maximum number of iterations,the throughput rate varies from 3.81 to 9.19 Mbps according to different code rates.The resource consumption is 14.8k logic elements in FPGA,and 150,000 logic gates in ASIC,the power consumption is 8 milliwatts.