Multi-mode Ldpc Decoder Algorithm And Vlsi Realization

During the last decade, we have witnessed appearances of transmission standards for wireless communication,such as IEEE 802.11n,IEEE 802.16e,DVB-S2,DTMB and CMMB.All these transmission standards employ a Low-Density Parity-Check Codes as coding scheme:by adding some redundancy and proper coding of a signal, high transmission quality can be achieved even over noisy channels. Another important trend is that a single user terminal that will be capable of receiving signals of multiple different transmission standards.This triggers the need of so-called multi-standard LDPC decoders.In this paper, we aim to propose a flexible architecture which can support multiple code rates and variable code lengths and can decode any existing Block-LDPC codes, especially suitable for multi-standard schemes. In decoding algorithm part, by rearranging the decoding flow of TPMP algorithm and combining the basic arithmetic operations both in TPMP and TDMP algorithms, a dual-algorithm LDPC decoder scheme has been implemented, which means making best use of high decoding convergence rate in TDMP algorithm and achieving decoding flexibility in TPMP algorithm to decode any existing Block-LDPC codes. In decoder architecture part, a partially parallel architecture which has scalable data-path and can be programmed to execute computations in two decoding algorithms has been proposed. As low cost and high throughput have become critical in LDPC decoder, optimizations are performed both on algorithm and architecture by deploying other new techniques. The main contributions of this dissertation can be concluded as following:1)The decoding schedule of TPMP algorithm is rearranged to be convenient to share hardware resources with TDMP algorithm, including memory blocks, basic processing units and so on.Moreover, to make a good trade-off between decoding complexity and error correction performance, a Normalized Min-Sum (MSA) algorithm is adopted in check-node operations.2) By introducing an idea of specific micro-instruction, decoding procedure based on parity-check matrix was abstracted as a set of user-defined instructions.The code rate, code length, decoding algorithm and other parameter could be reconfigured according to the structure of Block-LDPC codes.For unstructured Block-LDPC codes, a method of sub-matrix dispatch is proposed to avoid data-collision when updating messages in variable/check nodes.3) A Reconfigurable Serial Processing Engine (RSPE) which has scalable data-path and can be programmed to perform computations both in TPMP algorithm and TDMP algorithm is proposed. Meanwhile, in order to achieve a maximum throughput, the RSPE can be configured to decode in different decoding mode with 6-stage pipeline. Furthermore, The basic processing units in RSPE are working by time-division multiplexing to increase Hardware Utilization Efficiency (HUE) and the unused processing units can be deactivated to reduce overall power consumption.4) To further improve area/power efficiency, a) only single-port register file memory is required by exclusive write/read operations and register-buffering, resulting in a reduction of 30% in area when compared with dual-port memory, b) a memory-sharing scheme has been deployed in two decoding algorithms when decoding in different mode, c) based on different code rate,50%～90% memory size on extrinsic messages are reduced by storing them in a compressed form, d) memory access rate can be reduced by data buffering to reduce power consumption.