Research On Encoder/Decoder Of AA-LDPC Codes Based On ASIP

Applied in many fields such as communication, broadcasting, etc, LDPC (Low density parity check) codes have become a strong competitor in future 4G communications due to its near Shannon limit performance and parallelism. As a kind of excellent correcting code, AA-LDPC codes have been applied in DTMB, WiMAX, etc. Though LDPC codes have the advantage of performance, there still exist large demand of hardware consumption and long latency bottlenecks. This paper focuses on the research of the LDPC codes in DTMB from encoding algorithms, decoding algorithms and ASIP architectures. The main contributions are as follows.1. This paper proposes a scaling factor quantization scheme for LDPC codes. By scaling message of nodes, the scheme allows the integer part of message to include more information, and it can lower the effect of quantization saturation. Messages of nodes are quantized with (q,0). Due to the application of integer part instead of complex floating point operation, the hardware complexity is significantly reduced. Simulation in normalized Min-Sum displays an implementation loss of about 0.1 dB compared with floating performance.2. This paper proposed two stopping criteria for AA-LDPC codes, (a) Part check algorithm only checks one block row of H matrix at a time, which lowers the command of bandwidth of H matrix. It can save the bandwidth by 97%,95% and 90% with respect to 0.4,0.6 and 0.8. Correspondingly, the computation complexity is also lowered. Simulation dedicates that the performance approximates to the performance of standard check stopping criterion, (b) Two-thresholds stopping criterion uses the feature of LDPC decoding algorithm to generate thresholds at low and high Eb/NO, respectively. Only two thresholds are demanded to stop iterative by simulations, which reduce computation complexity. Furthermore, it has been demonstrated by simulations that the proposed stopping criterion can save iterations up to 90% compared with FIXED and outperformance HDA, SCR and CMM.3. A LDPC decoder in DTMB based on ASIP is designed. The processor adopts five-stage pipeline RISC MCU. Compared with GPP and ASIC, this decoder gets better tradeoff between cost and flexibility. A pre-access method for checking node memory is proposed, which can reduce data width by 75% and lower complexity. At Xilinx XC4VLX160, the throughput can achieve 134Mbps at 80MHz.4. An LDPC encoder in DTMB based on ASIP is designed. By adopting two processors and extracting special instructions, the encoder based on ASIP achieves high throughput of 240Mbps at 80MHz.5. This paper simulates the algorithm and ASIP architecture in the system-level, and builds the FPGA platform based on Xilinx XC4VLX160 to verify the LDPC decoder. Results show that the proposed algorithm and LDPC decoder meets the command of DTMB.Though this paper focuses on the research of the LDPC codes in TDMB, the methods and results in this paper can also be applied to other AA-LDPC codes. Moreover, the research on ASIP is beneficial for ASIP design methodology.This dissertation work is supported by Foundation of Shanghai Science and Technology Committee on the project "Research on high-performance ASIP architecture based on LDPC" (No.08700741200), open project of Key Lab. of Wireless Sensor Network & Communication, Chinese Academy of Sciences "Research on ASIP architecture based on LDPC in wireless communications" and PHD Program Scholarship Fund of ECNU.