| During the last two decades, the world enter the information age, various information technologies emerge such as the fast-growing communication technology, which makes it possible for people to connect with each other everywhere at anytime. In order to meet the increasing demands on communication services, the communication technology has been one of the most important research areas in modern science and technologies. The main challenges include how to make full use of the finite resources in the frequency, time and space domain, and how to improve the reliability and security of transmission.There are various advanced communication technologies such as modulation and demodulation, channel estimation, equalization and channel coding, which improve the performance of communication systems significantly. As one of the channel code, LDPC code has superior error-correcting performance and has been employed in many digital communication systems. Research and innovation on this technology will accelerate the development of communication technologies dramatically. In this paper, we aim to study the optimization of LDPC decoding algorithms and VLSI implementation issues in order to reduce the hardware resource requirements and improve the configurable capability.As one of the most powerful error correction codes (ECC), LDPC code can be categorized into two kinds:1) LDPC Block Code (LDPC-BC), invented by Gallager in1962. It has superior error-correcting performance, only0.0045db loss to Shannon limit is reported with rate-1/2LDPC-BC code under BPSK modulation in prior art. Besides LDPC-BC codes have advantages of low error floor and low decoding complexity. LDPC-BC is adopted by many communication standards such as IEEE802.16e, IEEE802.11n, DVB-S2, DTMB and CMMB.2) LDPC Convolutional Code (LDPC-CC), which is introduced by Felstrom and Zigangirov in1999. It has advantages of simple encoding scheme, flexible code sizes and comparable performance to LDPC-BC. Beseids the start bits of a frame will have more excellent error correction performance LDPC-CC is more suitable for hand-held devices and networking systems and has promising future. LDPC-CC has been one of the research hotspots recently and has been adopted as one optional ECC in the draft of IEEE1901standard.In this paper, the decoding algorithms and architectures are optimized for LDPC-BC and LDPC-CC code respectively:1) For LDPC-BC code, the TDMP algorithm is modified to support both structured and unstructured LDPC-BC code efficiently, the memory requirements is reduced through extrinsic storage strategy optimization, the hardware resource is reduced by processing units and main decoding schedule optimization.2) For LDPC-CC code, by introducing layered decoding algorithms, the decoding convergence is improved and better error-correcting performance can be obtained with less processors. In addition, the extrinsic information is stored in the form of minimum value, sub-minimum value, index of minimum value, signs and product of sign instead of the traditional priori/extrinsic storage strategy, the memory bits and hardware resource is reduced significantly. With the optimization techniques above, the memory and hardware efficiency of the proposed decoders in this paper have been improvedTo verify the proposed techniques in this paper, based on SMIC0.13μm CMOS technology, two LDPC decoders have been designed:Decoder-I and Decoder-II. Decoder-I is a LDPC-BC decoder supporting both DTMB and CMMB standards. It’s verified by FPGA prototyping and post-layout simulation. Decoder-I occupies4.75mm2core area and can operate at200MHz. It attains365.7Mbps throughput, which is far more than the requirements of the two standards (CMMB,20.22Mbps; DTMB,40.6Mbps). Running at5iterations, the operating frequency can be scaled down to25MHz and50MHz to meet the peak data requirements of DTMB and CMMB, respectively. The estimated power by post-layout simulations is only48.4mW and130.9mW, respectively. Decoder-II is a LDPC-CC decoder supporting IEEE1901standard. It has been fabricated and measured. The core area is3.33mm2and the maximum measured clock frequency is180MHz, at which a throughput of300Mbps can be achieved and the requirements of IEEE1901standard is220Mb/s. The measured core power consumption of the decoder with180MHz operating frequency is:138mW at rate1/2,162mW at rate2/3,188.4mW at rate3/4and200.4mW at rate4/5。... |
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