Construction Of EG-LDPC Codes And Implementation Of Encoder And Decoder

The channel coding technology has been widely used in various communication systems. LDPC code is more popular for its advantages that include unique good error bit performance and the low complexity. LDPC error correcting capability is extremely strong and it can get closed to the Shannon limit. LDPC is especially suitable for complex channel conditions and long distance communication because of its high coding gain. Thus we can reduce the power of the transmitted signal, it brings low economic cost. So the parity check matrix construction of LDPC code and its hardware implementation were chosen as the theme by the paper. The paper describes the steps and the processing of the construction of the LDPC parity check matrix based on Euclidean geometry. The code EG-1023 LDPC is implemented on the Virtex-V FPGA platform. The decoding architecture adapts for all the EG-LDPC codes.Firstly, the processing of the construction of the EG-LDPC parity check matrix based on the Euclidean geometry is clarified in the first part of this paper. T he relationship between Euclidean geometry and the association vector is studied and the parity check matrix of EG-LDPC code is constructed by the association vector. The research shows that we can construct different code length and code rate LDPC codes with the different Euclidean geometric parameters. According to the different system requirements, different EG-LDPC codes can be selected. It is more flexible.Then, the paper has carried on a detailed analysis of the encoding and decoding algorithm of LDPC codes. The performance and complexity of the algorithm are compared and we find an encoding scheme for the EG-1023 LDPC code based on the generator polynomial with the characteristic of linear time encoding. It is really suitable for FPGA implementation. For the decoding, simulation and analysis of the EG-1023 code under different decoding algorithms are carried out, giving the bit error performance curves. We find that the Turbo-like message passing scheme has the fast convergence speed, good bit error rate performance and small gain loss of the fixed-point simulation. So the method is chosen as the hardware decoding algorithm.Finally, the encoder and decoder is implemented on FPGA platform Virtex-V with the Verilog. Simulation and actual test show that the encoder gives out the correct results. The decoder performance is good. Five iterations only spents 0.5ms. It can be applied to most of the applications. The decoding architecture is very flexible and suitable for various LDPC codes with different code length and code rate. Importantly the error loss and the decoding resource consumption are very small. The EG-1023 code and EG-4599 LDPC code consume the same memory resources. The using of parallel decoder can further improve the throughput.