Research On The Frequency Divider In The Frequency Synthesizer

Frequency synthesizers is mainly used to produce electronic systems need all kinds of high precision,high stability of frequency signal,is currently widely used in communication,radar,such as testing equipment,is the key to the equipment components.The frequency synthesizer usually consists of five parts: phase detector,charge mercury,loop filter,voltage controlled oscillator,frequency divider.The divider is located in a frequency synthesizers feedback branch,it works under the highest frequency,it is the power consumption of frequency synthesis is one of the biggest source of the power consumption of the whole system,its performance has a decisive role on the performance of frequency synthesizers.Based on the analysis of the basic structure of the frequency divider,the MOS Current Mode Logic(MCML)circuit is used as the basic structure of the frequency divider circuit.Papers on MCML optimization design was carried out on the basic logic unit,using the basic logic unit of the optimized circuit design by 4/5 frequency division of synchronous frequency divider and four points of the asynchronous divider chain constitutes 16/17 of the dual-mode front divider.In order to reduce the loss of speed,the Latch is improved by analyzing the influence of the parasitic capacitance caused by the separate design logic gate.Single-phase clock(TSPC)circuit and draw lessons from the true source coupling level(SCL)circuit of the experience,to integrate the logical "or" the door on the latch,and applied to the dual mode in front divider,the design not only reduced the number of tubes,improves the speed of the frequency divider,also reduce the chip area,also reduce the noise and power consumption of the system.The simulation results show that the speed increases by 20%~30% by using the d-trigger of this integrated "or" door.Paper based on SMIC 0.13 ?m standard CMOS process,the power supply voltage of 1.2 V,the tail current Iss of 50 ?A,the output voltage swing is 0.5 V,the input signal is 500 MHz,the clock signal of 1 GHz,using cadence simulation.The results show that the circuit function is correct,and the maximum working frequency of 16/17 dual-mode prefrequency divider is up to 20 GHz,and the power consumption is only 0.66 mW.In the end,the layout design of the dual-mode prefrequency divider circuit is considered in terms of the matching of the device,the antenna effect and the Angle of reducing the substrate noise.