Research And Design Of Two-stage Low Power ADC Based On Ring Amplifier

In modern signal designing,the analog to digital converters(ADCs)are the important logic blocks,which play as an intermediary role between the analog and digital world data processing.And in the physical world,most of the signals are in analog nature,therefore ADC is crucial in the information acquisition system.Among many types of analog-to-digital converters,the successive approximation analog-to-digital converter(SAR ADC)occupies a vital part.Although the SAR ADC requires multiple comparison processes to complete a complete quantization,it is widely used in ultra-wideband wireless receivers,medical instruments,and digital imaging systems,due to its simple structure,low power consumption,small area,and good suitability for advanced CMOS processes.And in recent years,in order to meet the needs of high sampling rate and low power consumption,a variety of new technologies and new structures have been applied to SAR ADCs,which has made SAR ADCs develop from the low,medium sampling rates and medium precision to high-speed,medium-high precision now.SAR ADC has become the research focus and hot spot in the field of analog-to-digital converters.This paper studies and analyzes the key technologies of high-speed low-power SAR ADC.Compared with the traditional high-speed low-power analog-to-digital converter,in order to increase the speed of the SAR ADC,this design uses a two-stage structure to achieve parallel operation.In addition,because the traditional two-stage SAR ADC's inter-stage op-amp accounts for a large part of the entire ADC power consumption,in order to achieve the goal of low power consumption,this article uses a simple structure of the ring amplifier as an inter-stage op amp,which is effective to reduce the power consumption of the op-amp.This design implements a 12 bit two-stage SAR ADC with a sampling rate of 500MS/s under a 28 nm CMOS process and a power supply voltage of 0.9V.Using cadence for simulation,when the input signal frequency is the Nyquist frequency,the result shows ENOB is 10.3bit,SNDR is 63.76 dB,SFDR is 74.66 dB,power consumption is 6.09 mW,the Walden FoM of 9.66fJ/conv.-step.