Sample Rate Programmable Ultra-low Power SAR-ADC Design

The trends of miniaturization, low-power and high-precision for human signaldetection equipment tend to put a higher demand on the ADC design which plays the"Heart" role.There are two goals of the paper:Firstly, on the condition of using only conventional MOS transistors and without theaid of low-voltage technologies, the comparator with output offset releasing can achieve asimulation result of10bit resolution our SAR ADC, using just one pre-amplifier.Secondly, based on the counter structure, we select sampling rate to be programmableand make power consumption to decline proportionally. Meanwhile, the ENOB of SARADC decrease no more than0.5bit.There are four contribution contents of the paper:Firstly, we reviewed ADC in key performance indicators, introduced ADCs’mainstream architectures and to classify SAR ADCs (classification criteria is based on theDAC and comparator).Secondly, we had analyses focusing on the structural features of various DAC ofcharge redistribution structure, proposing the DAC setting of this paper. The design detailsrelates to the selection of the minimum capacitance.Thirdly, we introduced the timing of the SAR ADC in detail, given the specific circuitdiagram of each module and transistors’ parameters which include the DAC, thecomparator, the SAR logic module and the control module of sample rate programmabledesign.Fourthly, we outputted the CDL file under Cadence, had simulation with HSPICE andprocessed the simulation results on MATLAB to get the characteristic parameters of the ADC. The Analyzing and Comparison of FOM values had been done.Key results: Under1V supply voltage with sampling rate of2.52ksps, the simulationresults show an ENOB of9.14bit, an average power consumption of367nW, and FOM of258.1fJ/conversion-step. When the sampling rate is126sps, there is an ENOB of8.81bit,an average power consumption of21nW and FOM of371.3fJ/conversion-step.The study conclusions: on the basis of previous studies, the simulation research forSAR ADC proposed an ultra-low-power design and analyzed the low power indicators ofeach module, which provides a reference design for ultra-low power sensor of BAN (bodyarea network) applications.