Research And Design Of High Speed Two-Step SAR ADC With Passive Transfer

High speed analog-to-digital converter(ADC)is widely used in communication,measurement and other fields.In traditional communication systems,flash ADC and pipeline ADC are the first choice of high-speed converter.In the advanced CMOS technology,the main challenge of analog circuit design is achieving high linearity,high speed and high dynamic range,as well as reducing the power supply voltage and power consumption.Based on the characteristics of circuit digitalization,successive approximation register(SAR)ADC has become a very competitive product,showing its advantages in the field of high-speed analog-to-digital conversion.Thanks to technological progress,single channel SAR ADC can achieve GHz level sampling rate.The time interleaved ADC with SAR ADC as the sub channel can reach the sampling rate of tens of GHz,which is the best choice in the field of ultra-high speed conversion.Improving the sampling rate,area efficiency and energy efficiency ratio of single channel SAR ADC can not only improve the performance of the whole time interleaving system,but also reduce the calibration workload and system cost by reducing the number of channels.In this paper,the structure of SAR ADC and two-step ADC are studied in detail.The traditional SAR ADC is limited by the characteristics of single-stage structure,so it has encountered a bottleneck to improve the sampling rate.In this paper,two high-speed and low-power two-step SAR ADCs are designed,which use passive transfer residual voltage technology to shorten the inter stage voltage transfer time.In the first 10 bit 1 GS/s SAR ADC,charge divider technology is used to provide reference voltage for the second stage DAC,which greatly reduces the second stage capacitance and improves speed.In 28 nm CMOS process,the simulation results show that the SNDR,SFDR and ENOB of ADC are 56 dB,70db and 9.1bit respectively at high frequency input.In the second 10 bit 900MS/s SAR ADC,a four input comparator is used to reduce the capacitance and realize the gain matching between stages.In 28 nm CMOS process,the ADC area is only 55?85?m2.The simulation results show that the SNDR,SFDR and ENOB of the ADC are 52.2dB,63.2dB and 8.39 bit respectively at 900MS/s sampling frequency and high frequency input.