Research On And Design Of Sub-65nm SRAM Stability

SRAM is an important part of computer system and play a important role in direct interface with CPU. The scaling CMOS techniques feature high SRAM performance, small area, and low power, while it poses the unfavourable effect on SRAM stability. Especially when CMOS technology goes beyond 65 nm node, SRAM stability encounter serioius challenges, inducing the great concerns of the world famous IC design and manufacturer corporations and research associations such as Intel, Renensas and MIT etc.This thesis research and analyse the process impact on SRAM stability,and present an DC voltage division technique to improve stablility.Lowering the word line voltage during SRAM read cycle can improve read stability.Lowering the cell voltage during write cycle can improve write stability.Compared to current techniques,the proposed method have features:①The programmable word line and cell voltage settings benefit precise control.②The cicuit implementation is easily integrated into SRAM.③Using SRAM internal timing avoid complex timing generation.④Area penalty is negligible.This proposed technique is used to 65nm SRAM design. It is composed of 8K bits,256 words depth, 32 bits width,64 word lines,128 columns and cell with area of 0.625um2.The stability improvement circuit accout for about 2% total layout area.The manufactured chips test report shows:The word line and cell voltatge could lower linearily accortding to SRAM operation voltage varying from 1.0V to 0.6V,which is just the feature of DC voltage division. With the programmable settings, the minimum write voltage can improve by 130mV to 170mV, meaning the write stability improvement by 15%. The extra power consumed by this technique is less than 1%.