0.25um High Performance SRAM Design Methodology Using Memory Compiler

In recent years, many IP vendors have been devoted to the development of memory compiler. The core competitiveness of SRAM compiler is the area and speed advantage. Facing more competitors, this paper proposes to use the design of two memory architectures in the same memory compiler for area and speed optimization. The result has achieved a chip area improvement of 20% smaller and a speed improvement of 15% faster than the comparable products in the industry and is considered the most competitive design in memory compiler.