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Research On Area Optimization Of CMOS Circuit Based On Logic Mapping

Posted on:2020-06-17Degree:MasterType:Thesis
Country:ChinaCandidate:Q YuFull Text:PDF
GTID:2428330626951256Subject:Engineering
Abstract/Summary:PDF Full Text Request
Logic mapping is a very important part of the logic synthesis process.Traditional mapping is based on standard cell library,but the limited number of cell circuits in the cell library limits the possibility of further optimization of the logic circuit.In addition,the emergence of new processes and new devices has also brought significant cost to the maintenance of cell library.Library-free mapping uses virtual libraries instead of standard cell libraries.The cell circuits used are generated on demand,thus breaking the limitations of traditional cell library mapping,which makes the circuit have further optimization space.In terms of logic circuit performance optimization,approximation computing is being used as a compromise,by sacrificing a portion of the computational accuracy in exchange for a significant increase in circuit performance.In this paper,the approximate computing technique is applied to the 4-bit approximation adder design to achieve the circuit area,and the area is further optimized using the Library-free mapping.This paper mainly includes the following three parts:1)An area estimation model based on And-Or-Invert Graph and logic effort was established.Logic effort is originally used to estimate the delay,but also can be used to estimate the area.In this paper,we use a correspondence between And-Or-Invert Graph and CMOS circuits to propose a method that can directly calculate the logical effort on the And-Or-Invert Graph,so as to estimate the area of the logic circuit.2)A hybrid algorithm based on dynamic programming and genetic algorithm is proposed as the coverage algorithm of Library-free mapping.Aiming at the problem that the traditional dynamic programming algorithm covers too long when solving large circuits,the hybrid algorithm sacrifices a small amount of optimization effect in exchange for a large increase in coverage speed.3)Using the genetic algorithm as the search algorithm,the area of the 4-bit approximation adder is greatly reduced.After applying the Library-free technology to the approximate calculation process,the area was further optimized and the feasibility of the Library-free technique was verified.
Keywords/Search Tags:Logic Optimization, Library-free Mapping, Logic Effort, Approximate Computing
PDF Full Text Request
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