| This thesis introduces a new approach to library-free logic synthesis (LFLS) of intellectual property (IP) blocks, with corresponding developments related to the generation, modeling, and optimization of virtual cells. Template cell structures for the virtual cell topology are first chosen as being AND-OR-INVERT and OR-AND-INVERT in function and implemented in a static CMOS configuration. These templates were then modeled using an enhanced logical effort model (ELEM), developed to address ultra-deep sub-micron (UDSM) effects. This model was implemented in MATLAB and compared with HSPICE simulations across 4 nanometer technology nodes; 90nm, 65nm, 45nm and 32nm, with good accuracy ranging from an average of 3.3% for simple gates and 6.9% for complex gates.;This model was then used to determine the ideal partitioning stack length criteria, or maximum number of NMOS and PMOS transistors connected serially, in order to ensure complex gate delay optimization vs. a simple cell implementation of the same function. The results show that depending on the technology node and template cell structure, more than one stack length criteria is possible to provide this optimization, a result not addressed in any of the literature.;Based on this result, and number of derived and tested heuristics, a new partitioning algorithm, dubbed Complementary Logic Partitioning or CLP, was developed. The cumulative rules and requirements for CLP was then automated into the CLP tool, and compared with the Synopsys Design Compiler software, as well as other library-free logic synthesis techniques. The results show that compared to the other LFLS techniques, CLP performs adequately, meeting or exceeding the alternative approach by an average of 30% in delay, with fluctuations in area comparison. In relation to the Synopsys software and the standard cell approach, the CLP tool decreases the delay of the benchmark designs by an average of 29%, with an average area increase of 18% when compared with Synopsys.;Finally, the ability of performing transistor size optimization was investigated. By enhancing a current process for optimization to address complex cells, an average energy savings of 25% and area savings of 30% is demonstrated, requiring only an average increase of 4% in delay. |
