| This work deals with creative approaches to map a design into customized CMOS complex gates by using a virtual library technique. In this technique, the performance of CMOS complex gates and the logic path derived from the transistor topology are used in guiding the synthesis process. The main components of the algorithm include timing driven logic transformation, logic partitioning, gate mapping and transistor re-ordering. The logic partitioning is a performance driven process, which efficiently clusters the logic tree into sub-trees subject to topology criteria. The gate mapping is to choose a CMOS topology for the clusters that provides minimum cost. Transistor reordering improves the timing by adjusting the position of transistors to meet the time budget for critical paths.; The proposed mapping algorithm was used in combination with a topology-based performance estimation model to synthesize some of the MCNC91 benchmarks using the virtual library technique. The results show that the algorithm can achieve 42% improvement in area and 43% improvement in power compared to synthesis done by Synposys' Design Analyzer. (Abstract shortened by UMI.)... |
