Logic-level Power Optimization Method Based On Approximate Calculation

With the advancement of integrated circuits,applications such as computer vision,artificial intelligence,and big data have been developed.However,with the development of these applications,higher requirements are placed on the computing power of the underlying hardware.So how to meet the application layer requirements in the existing technology is one of the current research priorities of integrated circuits.Approximate calculation is a design method that exchanges the loss precision for power,area and delay optimization.Because the loss calculation accuracy does not affect the final output in some specific applications,the approximate calculation has certain practical application value and potential.Application prospects.According to the characteristics of Boolean and Reed-Muller(RM)logic,this paper combines the approximate calculation method to optimize the circuit.The research content has the following two aspects:(1)An approximate optimization method based on an approximate calculation of an RM(Incompletely Specified Fixed Polarity Reed-Muller,ISFPRM)function including an incompletely determined term.In this method,the polarity conversion speed is improved by the parallel list method and the disjoint term representation,and the power consumption calculation speed is improved by the formula method instead of the low power decomposition method,and the optimal approximate circuit version is searched by the genetic algorithm.(2)Traditional Boolean(TB)logic optimization method based on approximation calculation.The method quickly anchors the position of the card by calculating the probability of each node signal,and cuts off the circuit structure by forward simplification and reverse simplification techniques.Finally,the version of the high-quality approximation circuit is obtained by the maximum profit point calculation method.In addition,the optimization effect of single logic is limited.It is found that the dual logic representation circuit composed of RM+TB can achieve better results,so this paper will optimize the power consumption according to the characteristics of the dual logic circuit.The main research contents are:(3)Power optimization method for dual logic circuits.The possibility of cascading structures of the same type and optimization of mirror structures is discussed.The specific implementation: by looking for the pattern diagram in AXIOG(And-Xor-Or-Inverter Graph,AXIOG),according to the characteristics of each pattern diagram,combined with the power consumption of the reconstructed structure for pattern matching,select the optimal match figure.