The Design Of Low Leakage Power Standard Cell Package Based On The Dual Logic Mapping Technology

The advancement of semiconductor manufacturing process, masks the smallest craft and smaller in size,resulting in increased leakage power consumption. Since0.13μm process begins, the proportion of the leakagepower consumption in the total circuit power consumption can not be ignored. At present, regarding reducing theleakage, various techniques have been recommended such as channel length offset, dual threshold techniques.However, these techniques are seldom applied to the design of the standard cell library. Furthermore, compared toconventional Boolean logic circuits, approximately50%of the circuits adopt the Reed-Muller (RM) logic toimplement the available area as well as the significant improvement of power consumption. Therefore, it will bean extremely meaningful and valuable work to apply the leakage power consumption reduction technology andRM logic circuits to optimize the design of standard cell library. In view of that, this thesis chooses SMIC0.13μmstandard cell library as the research object, under the circumstance of a comprehensive analysis of the currentresearch both at home and abroad, the software produced by Cadence and Synopsys are mainly adopted toresearch the design methods of leakage-power reduction techniques in the standard cell library through thesimulation test on the leakage power consumption of various unit circuits; through the analysis of multipleXOR/XNOR gates of different structures, a low-power XOR/XNOR gate circuit is proposed and a variety of RMlogic compound-gate circuits are designed. In the end, a dual-logic standard unit package of low leakage powerconsumption is designed on the basis of layout design, cell characterization and layout information extraction.The main contents of this thesis are:1. Applied research in the standard cell leakage power consumption is reduced. On the basis of themechanism of the circuit on the analysis of leakage power consumption by using HSPICE simulation software forbasic gate channel length biasing techniques and the use of dual-threshold circuit delay after technology leakagepower and leakage power consumption delay product surveys and other features of the device channel length foroptimal value and dual-threshold devices in the circuit design and the use of the channel length biasing techniquesfor standard cell library basic gate leakage power optimization.2. Design RM composite logic gate cell. By analyzing the XOR gates to compare different structures,features the same or gates, inverters is proposed based on an improved structure of the XOR, XNOR gate, andbased on this XOR, XNOR gate circuit is completed with a variety of RM composite design logic gate circuit.3. The design of low leakage power standard cell package. This thesis uses the Cadence software to completethe circuit layout and physical information extraction of standard cell and uses Liberty NCX characterizedstandard cell. Finally, the low leakage power dual logic standard cell package based on RM composite logic gateis got.4. The study of dual logic mapping techniques. Based on the technical mapping principle study, through theanalysis of synthesize, extract and then the combined effect of the policy on the consolidated results of the doublelogic mapping method is proposed based on a special constraint command. Finally, an8-order FIR digital filterfrom logic synthesis to layout design to achieve low leakage power consumption of this design of the doublestandard cell logic package validated, the results show that the design of low-power standard cell leakage package can be EDA tools used in the optimization of circuit area and power consumption is reduced leakage achievedcertain results.