| This report presents the design, the delay estimation methodology and the performance of multi-GHz energy-efficient asynchronous pipelined circuit using MOS current-mode logic. Asynchronous MCML pipelined circuits combine the potential advantages of MCML and asynchronous circuits to improve performance, to reduce energy consumption, and to provide an analog-friendly environment. An MCML C-element gate and an MCML double-edge triggered flip-flop are introduced to implement micropipeline circuits. Furthermore, a delay estimation methodology for single-level and double-level MCML gates is proposed to help obtain the associated transistor sizes. An asynchronous MCML FIFO, implemented as a micropipeline structure, demonstrates a throughput of 4 GHz and dissipates 3.65 mW The MCML micropipeline control circuit for this FIFO dissipates up to four times less energy compared to a conventional CMOS control circuit with the same throughput. Our asychronous MCML implementation of a 4-bit Brent-Kung carry lookahead adder runs at 2 GHz and dissipates 17.6 mW, while its 8-bit version runs at 0.45 GHz and dissipates 51.37 mW. The simulated results are based on extracted post-layout simulations. All circuits are implemented in a standard 0.18 mum CMOS technology. |
