Design Of Ferroelectric Memory Read-write Circuit

With the rapid development of the information society,the demand for data storage is increasing.Although ROM memory can achieve large capacity,but the read and write speed is not very fast.RAM memory will lose data after power off.Under this background,Ferroelectric memory has begun to emerge.Ferroelectric memory has a read and write speed close to RAM memory.Due to the residual polarization,the data still exists after power off.Ferroelectric memory is inherently resistant to radiation,so it is used in a wide range of fields.The purpose of the thesis is to design a set of read-write circuits suitable for 2T2 C basic ferroelectric memory cells.Specifically,it includes the following sub-modules: address transition detection circuit,decoding circuit,control signal generation circuit,sensitive amplifier,bidirectional data circuit,latch circuit,etc.This thesis first outlines the characteristics of ferroelectric materials and the microscopic mechanism of ferroelectric materials used to store "1" and "0",and explains the selection principles of ferroelectric materials.Subsequently,the advantages and disadvantages of several basic memory cell types of ferroelectric memory are compared,and the read and write timings of the basic memory cells used are introduced in detail.In the theoretical analysis,the external input timing requirements of 1Mbits ferroelectric memory are first introduced.The ferroelectric memory can read or write basic memory cells under different external timing requirements.Subsequently,the read-write principle of the ferroelectric memory read-write circuit is explained,and the working process of the page mode in the ferroelectric memory is introduced.The page mode greatly improves the access speed of continuous addresses.After introducing the principle of reading and writing,the specific circuit module design is carried out according to the timing requirements.First,the overall framework of the read-write circuit is proposed,and then the circuits in the framework are divided into data channels and address channels for discussion,and specific theoretical analysis and circuit design are carried out.Then the simulation verification of the whole circuit was carried out.The results show that the read-write circuit can successfully access the corresponding memory cell under external timing.During the read access,the time from the chip select signal to the data readout is 35 ns,and the page access time in page mode is 10.5ns.The read-write circuit designed in this thesis adopts a control signal generating circuit with strong portability,which can generate arbitrary control signals and can ensure the normal reading and writing.After proper modification of the timing,it can be applied to ferroelectric memories with different capacities and different types.