Optimization Design Of Read-Write Circuits For Cim Implementation Based On STT-MRAM

With the rapid development of the Internet of Things and artificial intelligence,it is more and more difficult for the existing hardware structure to process billions of data.In conventional Von-Neumann architectures,the well-known “memory wall” becomes a critical barrier to limit bandwidth.In order to solve this problem,computing in memory(CIM)within STT-MRAM(Spin Transfer Torque Magnetic Random access memory)emerges gradually.The basic idea is that instead of moving all data to the processor,it pre-processes data then transfers processed data to CPU.However,CIM requires multiple memory units in parallel,resulting in higher reading error rate.In this paper,a novel dual-reference sensing scheme(NDRS)is proposed for hybrid CMOS/MTJ logic circuits.By exploiting novel precharge scheme and adding inverter to amplify signals,NDRS scheme can improve CIM reliability significantly.This paper carried out the following five aspects of work:1.Based on the 40 nm Magnetic Tunnel Junction model,the optimization design and simulation verification of STT-MRAM writing circuit were completed.The write circuit is an important part of STT-MRAM structure.It is very important for ordinary reading and CIM by sensing amplifier to have high write speed and write reliability.In addition,the initialization of dual-reference sensing circuit for CIM requires the write circuit to perform.Therefore,the third chapter has done a lot of research on the writing circuit.Firstly,paper carried out simulation to verify write mechanism in a single unit,finding out that the influence of temperature and supply voltage on the writing time.Besides,paper completed the optimization design of word line transistor and writing drive circuit in high-speed writing pulse.Secondly,aiming at the basic memory block(M×N memory block)in the memory computing array,paper finished the optimal parameter design of the memory array associated transistors under the condition of 10 ns write pulse by simulation of write drive,transfer gate transistor,temperature and power supply voltage.The simulation results show that the design results can reduce the write power to ?2p J when the write speed of STT-MRAM is less than 10 ns.2.Based on the 40 nm MTJ model,the optimization design and simulation verification of STT-MRAM reading circuit are completed.Because CIM will reduce the sensing margin,which has a bad effect on the reliability of the sensing amplifier,it is necessary to design a high sensitivity amplifier.Firstly,based on the full sensing margin pre-charge sensing amplifier structure,paper designed a novel better performance sensing amplifier without reducing the reliability which can be used for high parasitic effect circuit.A lot of simulation shows that it can reduce read latency time,and 486.5% power consumption.3.In view of low sensing margin problem of CIM based on the STT-MRAM,paper improved the reliability of dynamic dual-reference sensing circuit.Simulation results show that compared with the dynamic dual-reference sensing circuit,reliability enhanced dynamic dual-reference sensing circuit increase reliability margin by 59.4%.4.Paper proposed a novel dual-reference sensing scheme(NDRS)for hybrid CMOS/MTJ logic circuits.By exploiting novel precharge scheme and adding inverter to amplify signals,NDRS scheme can improve CIM sensing margin and reliability significantly.The simulation results show that compared with the full sensing margin pre-charge sensing amplifier,the CIM implementation speed and CIM reliability of NDRS are increased by757.1% and 21.98% respectively.Compared with separated precharge sensing amplifier,the CIM reliability of NDRS is improved by 67.25%.5.After an in-depth study of STT-MRAM read-write circuit,the CIM read-write circuit in array is completed.A symmetric reading scheme of blocks is designed to solve the problem that precharged sensing amplifier and separated sensing amplifier cannot read correctly due to the parasitic effect of array.In summary,the simulation results of the paper meet the design requirements,but also provide an effective scheme for the high-speed and high reliability optimization design of CIM within STT-MRAM.