Design Of 20GSPS And 12bits Acquisition Module Based On TIADC

Since mankind entered the information age,electronic information technology has developed rapidly.now the electrical signals in electronic systems are becoming more and more complex and the frequency is getting higher and higher.This requires that the sampling rate and resolution of acquisition systems such as oscilloscopes become higher.However,as the core of the acquisition system,China's high-speed analog-to-digital converter(ADC)mainly depends on foreign imports,and many indicators of available ADC devices are limited,which hinders the development of the acquisition system.In order to break the limitation of single-chip ADC and improve the sampling rate,it is a feasible scheme to build a parallel acquisition system based on time-interleaved ADCs(TIADC)structure.TIADC structure requires multiple ADCs to sample one analog signal synchronously,stagger the sampling time with each other at fixed time,and then assemble the data according to the sequence of sampling.Therefore,the TIADC structure has high requirements on the synchronization accuracy between ADCs,and also leads to difficulties in clock circuit design.In addition,due to the control accuracy of sampling time and individual differences of ADCs,data from different ADCs will have inconsistencies in gain,offset and phase,namely TIADC mismatch error,thus reducing the performance of the acquisition system.This thesis focuses on the above issues and adopts the following solutions:(1)Two 12 bit and 10 GSPS ADC were selected to build the TIADC system,and the synchronous clock generation circuit was designed by cascading two clock generation chips to meet the clock and synchronization signal requirements of ADCs and other devices.Then the data receiving and merging module is designed based on JESD204 protocol,which realizes the high-speed data reception of two ADC.Acquisition synchronization is the key prerequisite for the realization of TIADC,so the problem of synchronization between ADCs is solved by realizing the deterministic delay of JESD204 interface.(2)In order to reduce the mismatch error of TIADC system,a coarse error correction method is designed: with the input of single tone signal,sinusoidal fitting algorithm is used to estimate the mismatch error value,and then analog and digital compensation methods are used to complete the coarse error correction.However,for the 8 GHz wideband system in this thesis,the phenomenon that the mismatch error will change with the input frequency cannot be ignored.Therefore,a fine error correction method is designed based on the frequency response mismatch theory.In order to ensure real-time processing,digital filtering is completed in FPGA,and Fast Fourier Transform(FFT)and inverse Transform are used to realize frequency domain processing,which ensures realtime performance and saves FPGA resources.In this thesis,a 12 bit,20 GSPS,8 GHz acquisition module is successfully implemented based on the TIADC structure.Combined with the mismatch error correction method designed in this thesis,the SFDR in the 0-8 GHz frequency reaches more than 40 d B and the ENOB reaches more than 6 bit.