Hardware Design Of 12bit High-speed Data Acquisitionmodule Based On TIADC

With the vigorous development of the integrated circuit industry,the difficulty of signal detection has become increasingly complex.In order to better complete the task of testing and analyzing more complex signals,higher requirements are placed on data acquisition systems with high bandwidth,high sampling rate,and high resolution.Is gradually occupying the market share,becoming an important part of electronic measuring instruments.Compared with traditional parallel transmission,JESD204 B serial transmission protocol has obvious speed advantage.It is widely used in single-chip analog-to-digital converter(ADC),but rarely studied in time-interleaved sampling(TIADC)system.The research contents of this article are as follows:1)Complete the overall design of the hardware framework of the TIADC acquisition module based on 10 GSPS.Through research on TIADC technology,the overall framework of 10 GSPS data acquisition module is designed.And carry on detailed design analysis to the key circuit module,give the design scheme of each module.2)Complete the hardware circuit design of the data acquisition module.Design a stable and reliable power supply scheme based on switching power supply and linear power supply;complete the selection of key devices including FPGA and ADC and phase-locked loop,and design the peripheral configuration circuit of ADC,FPGA and phase-locked loop;complete the serial protocol JESD204 B clock hardware scheme design;complete the hardware design of mass storage.3)Complete the design of high-speed data receiving and processing module.Design a high-speed data reception synchronization scheme using the JESD204 B serial protocol,and use its deterministic delay synchronization scheme of subclass 1 of its protocol to achieve single-channel multi-link synchronization and multi-device synchronization.Complete the functional design of data flattening,digital triggering,parallel sampling and waveform averaging to realize the correct reconstruction and display of waveforms.4)Complete the inconsistent study of the multi-channel frequency response of the 10 GSPS system.It is proposed to analyze the frequency response of the multi-channel system and to study an error reconstruction and error correction method based on timevarying filtering.The robustness and real-time performance of the system finally achieve high-precision correction of broadband signal acquisition by the system,and the algorithm is implemented inside the FPGA,and the feasibility of the method is verified.Through the debugging of the acquisition module and the test of the overall performance,the main indicators such as the real-time sampling rate,analog bandwidth and effective number of bits of the 10 GSPS oscilloscope data acquisition module designed in this paper have reached the design requirements,and the performance of the acquisition system and TIADC technology have reached the domestic leading level.