Research And Implementation Of Low Power MCU Storage Systems

With the rapid development of the semiconductor industry,the integrated circuit industry has received extensive attention from the state and society in recent years.The development of the Internet of Things,intelligence and big data has prompted MCUs to quickly enter thousands of households and play in social public life.The lack of roles,while at the same time,requires MCUs to have higher and higher performance,smaller and smaller areas,and lower and lower power consumption,this seemingly opposite but unified requirement makes power consumption a subject of much attention and focus.Based on the low-power MCU using ARM Cortex-M0+ core,this paper designs a storage system using multi-path set associative mapping mode Cache.The Keil+VCS software and hardware co-simulation verification platform is used to verify the function of the whole design.In this design,Cache and Flash controller are the core components of the storage system,which is the key part of this design.After considering a variety of factors,the Cache design decided to adopt a four-way set associative,16-word/line mapping mode,random replacement strategy,and hybrid Cache design.The design of the Flash controller section not only adds support for off-chip Flash single/multiple load mode switching control,but also adds CRC program verification.The addition of the previous function selects the four-way loading mode when the kernel access cache is missing,which greatly reduces the waiting time of the kernel,and the autonomous selection control that can be turned on/off also increases the flexibility of the function.The CRC program verification adopts five times of load failure automatic restart mechanism,which can effectively ensure the reliability of program loading,reduce the occurrence of program running errors caused by program loading errors,and the logic control of this function is simple,only the first and last bit check is adopted.The cost of the MCU's power and area is almost negligible.The memory system designed in this paper is directly attached to the AHB highspeed bus of the low-power MCU general-purpose architecture.In the full-speed operation mode,the design is compared with the MCU that uses 128 kB large-capacity SRAM in the design part of the storage system before the improvement.In the same evaluation environment,the overall power consumption can be reduced by 84.89%.The power consumption can be reduced by 74.50% from the storage system.This can also fully indicate the factor of the area.The use of large-capacity SRAM requires the system to sacrifice huge work.Consumption.This design uses four 512 B small capacity(2kB)SRAM to form the storage part of the Cache.The four-way group association strategy increases the local conduction control,and each time the effective access only the SRAM that is hit,compared with the full turn-on of the 128 kB SRAM,the dynamic power consumption is reduced by about 95%.