The Realization Of Automation Of Power-off Domains' Boundary Check In Low Power Verification Based On UPF

With the decrease of the size of chip technology,power d issipation problem is becoming more and more important.O n the basis of traditional design methods,low power design methods are increasingly applied to chip design.Verification is a very important step for baseband design.In low power design,it is required that the power down domains need to be powered on from a safe state.When a domain is powered on,isolation among domains is released.The boundary of power down domains may transit x state.The transmission of x state can result in signals confusion.It can also result in pn junction's breakover in implementation and leakage current.Therefore it is necessary to check the power-off domains' boundary for x state.For this verification point,we usually add check process to simulation.This paper elaborates the low power design and verification by a simple module.The design consists of code design,simulation and boundary check scripts.When the designs are complex or there are some other designs,it is a waste of resources if we write the check scripts by manual operation.And according to verification methodology,automation is preferred.Based on the theory of low power design and verification,this paper designs an automation flow for boundary check of power-off domains for low power verification of 3G module of baseband chip.This flow includes collection of lower power design information,information analysis and processing,functions to check boundary.This flow can automatically check the power-off domains' boundary.When the power-off domains are powered on,the isolation enable signal is the trigger of boundary check and the flow can locate to the domain boundary to check if there is any x state.In addition,the automation flow is based on the lower power design method and is tested in many mod ules in order to ensure the correctness.The automation of power-off domain's boundary check when it is powered on is an optimization of lower power verification flow.The automation flow is not only suitable for the 3G module mentioned in the paper,but it is also suitable to other lower power designs.It can analyze lower power design,collect lower power design information and generate check scripts.The information and scripts can be used in simulation and check the power-off domains' boundary when the y are powered up automatically.The automation flow is suitable to most designs.It can meet the verification requirement for automation,reduce resources and improve the accuracy of verification.