Verification For Bus System Of A SOC

One feature of SOC(system on a chip) design is IP reusability, which assure the shorter time for empoldering . Because of a mass of use of basic verified module, synthesize of modules Just as the design of bus system, have been more outstanding.With the development of integrated circuit(IC), verification has become the most important part of IC design. More verification method come into use, including random test, coverage-driven verifation and so on, but all have some shortage.In this paper, we use a simulation-based method that use coverage-driven. At first we use constrained-random vector to simulate, then analysis the coverage when up to some end condition. If it has simulated for long time, we reconstrain the verification vector and simulate again; if it has reached established coverage, we generate test vector handmade at last for the uncoveraged part. We use this method to verify a SOC system. At first we divide the system into little parts and verify them and then verify them all. We get a satisfied result with less effort by reducing the time of simulation effectively.This paper uses symbolic model check to verify the bus system. We use virtual clock to take the place of original clock to solve multi-clock domain problem and synthesize the complexity. Then we reduce the module by using constrain useless values, dividing the modules. At last we find some bugs that is hard to find with simulation verification.