Cache Of .32-bit Embedded Processor Design

In this paper, we focus on the design of a Cache system for 32 bits embedded microprocessor."ENOD" is a process with 32bits, in accord with IEEE-1754 (SPARCVS) configuration. ENOD have the balance with price and high reliability. It uses SPARC V8 instruct system.Cache system is the important parts of the processer. The architecture of this Cache system is "Harvard", separated with istruct Cache and data Cache. In this architecture, there have no interferes which made by data citation and instruct citation. By this way, we can read data and instruct in the same time. And improve the speed of processe. Nay, "ENOD" use pipelining to reduce the instruct cycle. And improve the speed of processe more. The Cache system include three parts: instruct Cache, data Cache and data interface. We also focus on low power design. We propose a sequential access procedure to reduce the power consumption of set-associative Cache memory. Simulate the design in three levels: module,sub system and top."ENOD" is a complex microprocessor system. This thesis has contributed a lot to the designing of embedded microprocessor with full copyrights. Moreover, it provides an optional microprocessor core for urgent need in aviation field.