The Design Optimization Of L1 Cache Controller And System Level Verification Methodology Research In YHFT-DX

YHFT-DX is a 32-bit fixed-point high performance DSP based on VLIW architecture. Its CPU works at the frequency of 600MHz with the performance as high as 4800 million instructions per second (MIPS). Inorder to solve the problem of"Memory Wall", it has"Two-level Cache and RAM on-chip"structure, and its level-one cache (L1) system including level-one program cache and level-one data cache will run at 600MHz as the same as CPU.According to the design requirement of the YHFT-DX project, this paper finished the design optimization, synthesis and verification of L1 controller with standard cell based semi-custom design flow. The result of the static timing analysis shows that the delay of the critical path is 1.61 ns, which fulfils the design goal of 600MHz. The main work and contributions of this paper are as follows:First, this paper optimized the design with multi-methods at arithmetic structure level, RTL code level, circuit level, and floor-plan stage for timing requirement. The delay of the longest path of L1 program cache and L1 data cache are reduced by 29.7% and 22.2% respectively.Second, partitioned cache architectures, clock-gating and dual threshold CMOS techniques were introduced for low power design. As the result of the experiments in this paper shows, L1-program-cache's dynamic power, leakage power and area are reduced by 30.2%, 74%, and 4% respectively, while L1-data-cache's dynamic power, leakage power, area are reduced by 33.6%, 54.3% and 5.8% respectively.Third, this paper finished synthesis, function and timing verification of L1. By inserting assertions in simulation environment, and developing test vectors based on function coverage in model level verification, as well as simulating some popular large benchmarks in system level verification, the correctness of design was ensured well.Four, this paper introduced a good verification method based on memory monitoring for system level verification and this method provides advanced verification efficiency and quality in YHFT-DX.