Research On Design And Verification Of Cache For A 32-bit DSP

Digital Signal Processor (DSP) has been widely used in communication systems, controllers, military electronics and household appliances. With the rapid development of integrated circuit technology, the speed of CPUs is increased much more quickly than that of memories, creating a bottleneck between them. In practical systems, cache is usually adopted to solve this problem. This thesis is based on a DSP design project in XX research institute, including two parts of work: cache controller design and cache memory design. The cache controller design adopts the top-down ASIC design flow with module classification, verilog code programming and synthesis using Synopsys tools. The cache memory design adopts the full-custom design flow, and the emphasis is put on the circuit-level design.In order to improve the efficiency of data processing, the cache contoller uses the Harvard architecture. In the design of the cache controller of Harvard architecture, the 4-way associated mapping algorithm is adopted. The substutution algorithms are the stack algorithm the fake-LRU algorithm for instrucion and data caches, respectively. In the design the idea of deviding the Tag bank and Data bank into two levels is proposed to decrease the power consumption. Adjusting cache size dynamically by introducing the dynamical reconfiguration method can also lower the power consumption of the studied system. Verilog codes are synthesized by using the Synopsys software and 0.25μm CMOS process library. The area of the cache controller is 280000μm2 and the circuit speed is 5.7 ns, both satisfying the design reqirement.For the cache memory design, the optimization of the decoder is first studied to discrease the power consumption of the decoder. The design of memory cells is then performed. In order to increase the memory speed and discrease the power consumption, a kind of differential sensitivity amplifier on the basis of the positive feedback principle is designed. The dynamic power consumption of the designed cache memory measured in HSIM is 25 mW, and the key path delay is 2.4 ns and 2.7 ns for the reading- and writing-cycles, respectively, reaching the requirement of the design.