Design And Verification Of JX Processor's Instruction Cache

Cache has been an important functional component in the high performance microprocessor. It's size and speed has been a main criterion of evaluating microprocessor performance. In this paper, presents design and realization of JX microprocessor instruction cache and its TLB (translation look-aside buffer) on the basis of research of cache technology.JX microprocessor's TLB is organized as a 32-entry fully associative. The TLB supports 4Kbyte pages as well as 4Mbyte pages. The replace strategy of TLB is handled by the pseudo-LRU (Least Recently Used) mechanism. The TLB's line address storage array is composed of CAM (content address memory). The CAM cell designed is rapid with small size and simple structure. The output of CAM cell is applied to dynamic logic. The drive of CAM employs a sense difference amplifier via translate single port output format. The TLB's physics address storage array output employs domino logic. In a word, the main data path of TLB is maked up of dynamic logic, is representative of dynamic logic applied successfully. So the TLB run in high speed, the result of TLB's layout simulated in SPICE in 0.18μm CMOS technology shows that the delay of TLB address translation is less than 0.8ns.JX microprocessor's instruction caches are 16 Kbytes in size and organized as a 4-way set associative cache. There are 128 sets in each cache, each set containing 4 lines (each line has its own tag address). Each cache line is 32 bytes wide. The JX processor employs a pseudo-LRU replacement algorithm which requires three bits per set. The instruction caches can provide up to 32 bytes of raw code in per clock. The instruction caches tag of the JX microprocessor are dual ported, one port is dedicated to support snooping and the other port is used to line accesses. The snooping port cooperates with "valid-bit" cell maintains caches consistency together. In order to improve caches work speed, in design, we employ two ways to optimize: one is to let caches and TLB work in parallel mode, the other is to optimize functional component. In addition, we added test path by testability design.At the end of this paper, a detailed scheme of functional verification on caches and TLB is drawn up.