Design And Verification For The Cache Based On ARM7TDMI

A Cache is a small, fast storage device between the CPU and the main memory. When CPU reads data or instructions, it saves data or instructions in Cache memory at the same time. So it can find the data or instructions in Cache memory when using them again. Cache memory is constructed with high-speed static random access memory (SRAM), managed with a unit called Cache Line. The Cycle time of SRAM can be as short as a few nanoseconds. This kind of performance can match the speed of microprocessor bus operation. This is the basic principle of the Cache.Different from desktop computers, the embedded computer system is applied in a special demand and focuses more on low cost, excellent performance, low power and high reliability of the system. Nowadays, with the development of the information technology, embedded computer system has been raising its performance to meet the needs of complicated signals and controls. The embedded processor is a core of the embedded system and its development will mostly improve the performance of electronic system.In embedded CPU family, ARM CPU is known for its high performance and low power dissipation. ARM7TDMI is one of the most popular CPU core in the series of ARM CPU. Without Cache, its performance is worse than ARM720T.The purpose of this thesis is to design a Cache based on ARM7TDMI and to realize the structure"ARM7TDMI+Cache", which can raise the performance of the embedded SoC system. Meanwhile, in this thesis a new approach is proposed to improve the performance of the bus when Cache miss happens. The design flow of front in Cache is described from its design in detail, functional verification and performance evaluation.