IP-Core Orinted Foorplanning And Power Pad Co-optimization

As the semiconductor technique enters the deep sub-micron stage, the supply voltage is further reduced, andthe metal interconnects occupy more chip area. Besides, the increasing IP cores are integrated into a single chip.All above factors make the IR drop (voltage drop) problem significant at the present stage. Excessive voltage dropmay cause the supply voltage can not meet the chip demand, degrade chip performance and even chip fails. Thetraditional SoC design flow deals with the IR drop problem at the post-layout stage, which may complex the flowand time consuming when the design does not meet the requirements. Therefore, the IR drop problem should bepaid more attention and solved effectively in the early physical design cycle.By exploring the SoC design flow and characteristics to optimize the voltage drop and accelerate the CPUtime, we propose a heuristic method which can optimize the floorplan and power pads simultaneously. Theproposed method is validated by testing the MCNC benchmark circuits.The thesis is mainly composed of thefollowing two sections:1. Floorplanning has a great impact on the current density distribution of power/ground network. In terms ofthe voltage drop problem, especially for those high current density IP cores, a current density awarefloorplanning algorithm based on fast simulated annealing is proposed. A modified SKB-tree is presented torepresent the floorplan, which favors to multi-objective optimization for multiple power pads placeddiagonally. From the results, although the method makes area, wirelength increase by2.07%and2.66%compared with the traditional floorplanning, the distance between high current density IP cores and powerpads is optimized by65.43%. Therefore, the effective resistance is reduced and the voltage drop is optimized.2. The tranditional SoC design flow is complex and low efficient. Considing the impact of power pad on thedistribution of power/ground network, the power pad allocation algorithm is proposed and embedded into thefloorplanning algorithm to achieve co-optimization. The volage drop estimation accuracy is improved byestablishing the close-to-real current density model. Compared to tranditional flow, there are no voltageviolations for all P/G nodes traded with7%and9%increases of the area and wirelength, respectively.Moreover, the maximum voltage drop is optimized up to83.7%. Experimental results show the proposedmethod can co-optimize the IP-core positions and power pad locations for voltage drop.