The Design Of TCP/IP Offload Engine For 10 Gigabit Ehernet And Hardware System Based On FPGA

With the rise of technologies such as 5G generation mobile communication,cloud computing,big data and the Internet of Things,the data flux has grown exponentially,and network bandwidth has also grown rapidly.At present,10 Gigabit Ethernet has been used widely.For CPU,how to handle network data that is getting faster and faster has become a major difficulty.The important solution to this difficulty is the TCP/IP offload engine technology(TOE technology),using special hardware equipment to process complex network data which can reduce the pressure of CPU and release its resources.However,the existing 10 Gigabit Ethernet TOE solution is not mature enough,and it has defects such as slow speed and incompatibility with standard protocols.Aiming at the current research and market demand,this paper designs a set of FPGA-based 10 Gigabit Ethernet TCP/IP offload engine and hardware system,implements standard TCP/IP protocol stack offload through FPGA hardware logic,and integrates security algorithms such as digital authentication to achieve high-speed and secure network data transmission and communication.The hardware system uses Xilinx XC7Z045 as the core processor,including four 10 Gigabit optical SFP+ interface,one PCIe 2.0×8 interface,and a high-speed storage space with four DDR3@1866Mbps and four DDR3@1066Mbps.The entire board contains 1190 electronic components,4118 connections,17 power supplies,and has 8 pairs of SFP+ differential traces with a maximum speed of 10.3125 Gbps,16 pairs of PCIe differential traces with a maximum speed of 5GTps and more than 180 DDR3 signals.Therefore,the hardware design of this system faces severe challenges of signal integrity,power integrity,and electromagnetic compatibility.With the help of theoretical calculations and simulation tools,this paper finally completes the hardware system design through strict impedance control,delay control and reasonable layout with 12-layer structure.At the same time,this desig uses the Verilog hardware description language to implement functions such as the standard TCP/IP protocol stack offloading,10 Gigabit Ethernet communication,PCIe interface communication,and DDR3 high-speed storage;uses embedded software programming to realize digital authentication that ensures the equipment security and transmission security;uses the software programming of the host computer to provide the system configuration,audit and the user-friendly interface.In summary,this paper completes the design of complex high-speed digital systems,FPGA hardware logic design,and host software design.It provides a solution for core server network hardware acceleration and is compatible with existing market standard equipment.Also it is easy to use and has a wide application prospects.