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The Design Of 10 Gigabit Network Monitor System Based On FPGA

Posted on:2022-05-10Degree:MasterType:Thesis
Country:ChinaCandidate:H WuFull Text:PDF
GTID:2518306479978459Subject:Communication and Information System
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At present,the number of network users and devices is increasing rapidly.The increase in network scale brings great security risks.A network monitor system is required to monitor the network,especially in campus network topology.However,both network monitoring technologies based on packet capture and traffic analysis have limitations.Combining the research status and application scenarios,this paper independently designs an FPGA-based 10 Gigabit network monitor system,aiming to make improvements in overall delay,monitoring comprehensiveness,hardware system design and resource occupancy.Combined with the PC and the web,the system architecture is based on the FPGA as the main and the ARM as a supplement,which are in the hardware system board.The self-designed hardware system board uses Xilinx's ZU7 CG as the core processor.The main peripherals on the board include nine DDR4@2400Mbps cache particles,one PCIe Gen3x8 interface,one 40 G optical port,two 10 G optical ports and two 1000 /100/10 M adaptive network port.The whole board contains 1485 components and 4670 connection points,and the highest signal rate is 10.3125 Gbps.In PCB design,the SI,PI and EMC of the high-speed digital system are fully considered.This paper combines theoretical analysis and simulation,strictly controls the layout and routing,and completes a 14-layer high-speed circuit board.Logic and software design are based on the hardware system board.In terms of FPGA,the functions of network data forwarding,protocol offloading,traffic statistics and data capture are realized through programming hardware logic module in Verilog HDL.In terms of ARM,the functions of traffic and application layer protocol analysis are realized through programming in C.In addition,the PCIe driver and PC Web-side interface are designed in this paper.In summary,this paper completes the system architecture design,high-speed hardware circuit design,FPGA logic design,software design,and system testing.The system in this paper completes the overall monitoring from the bottom layer protocol to the upper layer data,and the delay of network data forwarding,capturing and traffic statistics is less than 10 us,which can effectively reduce the resource occupancy rate by13%.The system makes up for the deficiencies of network monitoring equipment and the vacancies in domestic research and has application value which is suitable for a variety of applications.
Keywords/Search Tags:Network Monitor, High-speed Digital Hardware Design, FPGA, 10 Gigabit Ethernet
PDF Full Text Request
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