Design Of High Speed Serial Link Transmitter

With the increasing demand for data transmission in the information age,the transmission method of high-speed serial links has been used more and more widely because of its excellent transmission characteristics.With the further increase in data transmission rate,the four-level amplitude modulation technique(PAM-4)which has lower channel bandwidth requirements has received more and more attention in high-speed serial links.The goal of this thesis is to design a SerDes transmitter that supports both NRZ and PAM-4 signal modulation,and the maximum data transmission rate of the transmitter could reach 32Gb/s.To implement a high-speed SerDes transmitter that supports dual-mode,the design of transmitter architecture is very important.The traditional SerDes transmitter uses direct addition method to realize the feedforward equalization of signal,and the SerDes transmitter of this architecture consumes large power at high speed and is difficult to support multiple modes.In this thesis,a indirect look-up table method is used to implement the equalization of signal.The method utilizes lower speed parallel signals to look up the digital amplitude code,which will be converted to an analog output voltage by the driver.By moving the equalization work to a lower speed,this method can reduce power consumption and easily realize the modulation of both NRZ signal and PAM-4 signal.In this thesis,the transmitter architecture is designed based on the indirect look-up table method,and the solution of transmitter driver impedance matching and output voltage adjustment is discussed.What's more,the critical circuits such as serializer and clock path is designed and optimized aiming at low power and high speed in this thesis.The structure of 6-bit stacked voltage mode driver is used in this thesis,and the look-up table module could realize 4-tap feedforward equalization for NRZ signals and 2-tap feedforward equalization for PAM-4 signals.Accomplishing the circuit design,layout drawing and post-simulation of the SerDes transmitter,the transmitter can output 16Gb/s NRZ signal and32Gb/s PAM-4 signal respectively.It can be seen from the simulation results that the output signal eye diagram through a 15 dB insertion loss can be reopened under the effect of feedforward equalization,and the eye height is126 mV and 24 mV respectively.The energy efficiency of the NRZ signal and the PAM-4 signal is 2.38pJ/bit and 1.19pJ/bit,respectively.Compared with the reference papers in international conferencess in recent years,it can be found that the energy efficiency of the transmitter has been improved.