Design Of A 12.5Gbps High-speed SerDes Transmitter Based On Differential Encoding Technology

In the high speed data transmission system,the traditional parallel transmission technology can no longer meet the requirement of the system for the data transmission rate due to the limitations of timing synchronization and weak anti-interference ability.In order to improve the data transmission rate,high-speed Serializer/Deserializer(SerDes)technology came into being.Its main function is to convert multiple parallel low-speed signals into a serial high-speed signal for transmission.When the signal reaches the receiving end,the received high-speed signal is restored to the original parallel low-speed signal.Unlike traditional parallel transmission technology,SerDes does not need to transmit a synchronous clock during the transmission process,and the introduction of differential signals also enhances the signal's anti-interference and anti-noise capabilities while increasing the data transmission rate.Based on the above advantages,SerDes technology gradually replaces the traditional parallel transmission technology and becomes the mainstream of high-speed interface technology.Under this background,this thesis has made an in-depth study on the circuit structure of the currently popular high-speed SerDes transmitter,and adjusted and optimized each module circuit in the SerDes transmitter based on signal integrity.It is mainly reflected in the following aspects: firstly,for the data duty cycle distortion caused by the data synthesis clock when the process corner,voltage and temperature(PVT)changes,a current mode logic(CML)xor gate driver is proposed to complete the parallel-serial conversion and data output in the final stage;secondly,in order to achieve the purpose of original code output,the solution of adding a differential encoding circuit to the parallelserial conversion module is proposed for the first time,and through the logical relationship between the data,the data has completed the process of differential encoding and decoding in the transmitter;finally,this thesis also designs a low power consumption based on the traditional CML xor gate driver,and uses a dynamic load to achieve impedance matching between the driver and the transmission line.In this thesis,the 65 nm complementary metal oxide semiconductor(CMOS)process is used to complete the circuit design and corresponding layout of the SerDes transmitter front end.Post simulation results show that the transmitter data transmission speed reached 12.5Gbps.At this time,the overall power consumption of the transmitter is 39 m W,and the total output jitter is 0.06 UI,which is less than the 0.3UI required by the JESD204 B standard.