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Research On Key Technologies Of High-speed SerDes Transmitter

Posted on:2021-02-02Degree:MasterType:Thesis
Country:ChinaCandidate:B XieFull Text:PDF
GTID:2518306503974639Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
With the advent of the big data era,the explosive growth of data makes it difficult for traditional parallel data transmission methods to meet the transmission requirements due to the number of pins and clock synchronization.SerDes is a point-to-point serial communication method that uses a pair of differential transmission lines to transmit data at rates of up to tens of Gb/s or even hundreds of Gb/s.With its excellent transmission characteristics it gradually replaces traditional parallel data transmission methods.The low-pass characteristic of the channel due to dielectric loss and skin effect will attenuate the high-frequency part of the signal.The SerDes system uses various equalization methods to compensate for the different attenuation of the high-frequency and low-frequency part of the signal to ensure signal integrity during data transmission.This thesis introduces the research status of advanced SerDes at home and abroad in detail,then analyzes the theory of SerDes communication including time and frequency domain analysis of data transmission,noise analysis of NRZ and PAM4,analysis of jitter and reflection.Next,the two most important modules of high-speed serial communication are analyzed in detail: the feed-forward equalization and the driver.Detailed analysis of various structures is carried out and the principle is derived in detail.The advantages and disadvantages of various structures and their applicable environments are summarized.Finally,this thesis analyzes and verifies the transmitter's key modules based on the GF 22 nm process.A half-rate 16/32 Gb/s dual-mode transmitter using look-up table feed-forward equalization and source-series terminated driver is completed,which can provide 15/10 d B equalization at NRZ/PAM4 mode with the energy efficiency ratio of 3.1/1.55 p J/b.A quarter-rate 56Gb/s PAM4 transmitter using delay chain equalizer and current mode logic driver can provide 15 d B equalization with the energy efficiency ratio of 1.43 p J/b.The simulation results show that both the equalization capability and the energy efficiency ratio of the two transmitters have certain advantages compared to other advanced transmitters with the similar data rate.
Keywords/Search Tags:feed-forward equalization, source-series terminated, current mode logic, quarter-rate, low power
PDF Full Text Request
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