Design Of FPGA-based High-speed SerDes Serial Interface Module Transmitter

With the advent of high-speed information era,people have higher requirements for the operation and data transmission speed of various electronic products.In order to bring people a better application experience in the information age,circuit designers have proposed various implementations for high-speed interface data transmission.High-speed circuit transmission technology has now achieved rapid development from the initial multi-channel parallel data transmission to the serial interfaces with the ability to achieve higher speed.Among them,the high-speed Ser Des serial interface transmission technology that originates from the signal propagation in the communication field is the serial interface transmission technology with the fastest transmission speed and the highest data stability.It is being applied to more and more extensive fields.In the field of programmable logic chips,since the FPGA chip contains a wealth of logic resources,data transmission and reception is very large,so the high-speed Ser Des serial interface transmission technology has begun to be widely used in FPGA programmable logic circuit design.However,with the continuous increase of transmission speed,the integrity issue in the signal transmission process has gradually been concerned by designers.In order to guarantee high-quality transmission of signals,a specific design and planning of the Ser Des interface module is required,and the design of the transmitter module that carries the signal transmission task becomes particularly critical.This paper is based on the design of the transmitter of the high-speed Ser Des serial interface module in FPGA.After reviewing a large number of relevant high-speed interface circuit documentation,we first introduce channel systems for high-speed circuit transmission,and describe non-ideal factors such as reflection,ground bounce,crosstalk,loss,and jitter that are caused by channel characteristics in high-speed circuits.And put forward a variety of corresponding suppression measures.Then describe the overall structure of the Ser Des transmitter and the functions of the data processing auxiliary module,and study the key technologies designed and applied to the entire transmitter,such as 8B/10 B encoding,equalization techniques at the transmitter(de-emphasis),and differential interface transmission technologies.It also determined the implementation of the CML(current mode logic)circuit with a transmission rate of 2.5 Gbps to be achieved in this design.Based on the above theoretical analysis,a PRBS(pseudo-random binary code)circuit,a parallel-to-serial conversion circuit,a CML driver circuit,and an auxiliary circuit have been designed.Through the ISE digital logic simulation software and Virtuoso analog circuit software under the Cadence platform,the digital and analog parts of the circuit were designed and simulated.Finally,the final design circuit diagram,simulation waveform diagram and eye diagram are given.By analyzing the logic and signal quality of the final simulation results,it is determined that this design meets the design goals and parameter requirements for high-quality signal transmission with an expected transmission rate of 2.5 Gbps.At the end of this paper,a comprehensive summary of this design is made,and the problems and challenges that the design may face in the subsequent production and application are pointed out,and the insufficiency of the design is pointed out.The countermeasures that can be used for reference are also proposed.