Design And Implementation Of High Performance And Low Power Consumption SRAM In 65nm

With the development of microelectronics technology,the design for high-performance microprocessors has become more and more complex,among which the storage system,accounting for 70% of the total area of the microprocessor,is the core part of the microprocessor.The structure of High-speed Cache memory is one of the most important designs for the storage system.The modern microprocessor cache memory is made of two stage structures,which are the level-one cache(L1 Cache)and the level-two cache(L2 Cache).The speed of L1 Cache as fast as CPU,but the capacity is small(16KB ~ 32 KB,The capacity of a single bank is 4KB).As the centre of the storage system in the processor,L2 Cache memory is not only the critical paths for data throughput in CPU core Core Pac,but also the data sharing interface between Core Pac and the other processor.So the chip performance is critically affected by the performance of L2 Cache.The performance of microprocessors will be significantly improved by improving the performance of L2 Cache.L2 cache capacity is larger(512KB ~ 1MB),the capacity of single bank up to16KB),the speed is lower than L1 Cache(The speed of L2 Cache is 1.5 to 3 times slower than L1).The reading circuit is the critical path of the bank(SRAM),so the optimization on the critical path delay can improving the performance of ARAM,the large-capacity high-performance low-power memory banks(SRAM)to become the aims of SRAM designer.Firstly,in this article,In-depth study was made about the traditional structure of the SRAM circuit.As technology nodes becoming lower and lower,stability problems of the conventional 6T cell are increasingly severe,which also are the main bottleneck facing for the design of 6T cell today.With The emergence of separate read and write memory cells,the stability of reading and writing memory cell is increased,and noise margin is increased to improve the speed of reading and writing,especially the 8T cells have the most development potential in both area and stability.Secondly,in this article,the study and analysis of typical single-port sensitive amplification circuit shows that with the memory depth increasing,the full-swing single domino single-sense amplification structure's power and delay deteriorated sharply,pseudo-differential sense amplifier circuit and the coupling capacitance sense amplification circuit are very bad in controllability and stability as they easy be impacted by the PVT variation.And the latter has a larger coupling capacitors,occupied a large area.Combined with the problems of the traditional structure,this article proposed a circuit of single-port sense amplification that based on TBP structure,Its low BL precharge voltage,power consumption has been greatly improved,and with the capacity increased,performance and power haven't significant deterioration.its also having high stability and high reliability in the corner under a variety of process.Finally,from the viewpoint of both performance and power consumption,using full custom design method,under the 65 nm process,and based on the TBP single-port sense amplification structure,analyzed and designed a new memory banks that can be used for the L2 Cache,including 8T Cell,16 KB for capacity.The result of post-layout simulation showed that under the typical process corner(TT corner),compared with the same specification memory generated by memory compiler,at the cost of 37.65 percent of the area,the performance of SRAM based on TBP structure improved 24.96%,the power consumption reduced by 32.06%,which perfectly achieved the desired performance and power consumption requirements.