| The advent of the Internet of Things(Io T)has made people's pursuit of low-power,high-reliability chips increasingly prominent.Low-Voltage Static Random Access Memory(SRAM)is an indispensable part of low-power chips,due to its characteristics of high speed,high density,and high complexity,many test problems about SRAM should be solved urgently.Developing SRAM test solutions with high fault coverage and low area overhead has broad application prospects.In the thesis,the research on Low-Voltage 6T SRAM bitcell is conducted,the effect of Static Noise Margin(SNM)on Stability Faults is analyzed,which shows that increasing the word line voltage in the test mode can effectively expose the Stability Faults,while a parameterized model of Stability Faults is built for the injection of simulated Stability Faults and the index evaluation of Design For Testability(DFT)scheme.According to the theoretical research results,a DFT solution based on the modification of the word line structure is developed for the problem of Stability Faults detection in Low-Voltage 6T SRAM,which modifies the original word line structure,consists of a PMOS,a delay chain,two capacitors and an AND gate,while an external DFT test mode control signal test＿dft is added,the fault coverage can be effectively improved by cooperating with the proposed March Sta F algorithm.This thesis is based on TSMC 28 nm CMOS process,and adopts Tessent Memory BIST technology flow to implement the proposed DFT scheme on a low-power So C,and uses VCS+Finesim CoSimulation scheme for verification and analysis.The experimental data shows that the designed DFT circuit has an area overhead of about 1%(lower if considering the Wire Load Model),and the capability of detecting Stability Faults is improved by more than 89%(solves the problem that the test escape certainly occur on the drain of drive transistor);the designed MBIST optimization scheme ensures the fault coverage,while the area overhead is 0.7373% of all memories under test,while 0.0965% of the total area of the So C chip,the power consumption is 19.03μW,while 0.2424% of the total power consumption of the So C chip.Therefore,the proposed test scheme has good engineering practicality. |
