Design Of Single-ended Sense Amplifier For Static Random Access Memory Based On 22nm CMOS Process

With the continuous advancement of integrated circuit technology,Static Random Access Memory(SRAM)plays a more and more important role in System on Chip(So C).Because sense amplifier(SA)has the function of detecting small signal swings and realizing rapid amplification,it becomes an indispensable part of SRAM.It is the main restricting factor of SRAM's performance and power consumption.Under the low voltage,memory cells structures that are single-ended reading appears,and the differential SA is not compatible with it,so a new structure of single-ended SA is needed.Firstly,the commonly used differential SA and single-ended SA is summarized and compared.In view of the disadvantages of traditional pseudo-differential SA that the offset voltage is too large and the reference voltage generation circuit is needed,a pseudo-differential SA that eliminates the reference voltage is proposed in this thesis.By detecting and storing the polarity of the SA offset voltage,the offset voltage is reduced by half compared with the traditional pseudo-differential SA,and the design complexity caused by the reference voltage generating circuit is eliminated.Secondly,a half-voltage pre-charged SA is proposed,which uses the inverter's high gain characteristics.This solution requires only a small voltage difference to complete the detection.It eliminates the capacitance of the capacitive coupling SA,thereby reducing the area.The noise of the SA is analyzed,and a circuit to boost the array voltage is proposed,which not only improves the stability of the memory cell,but also speeds up the speed of bit-line discharge.Based on the TSMC 22 nm CMOS technology,taking the pseudo-differential SA that eliminates the reference voltage as the core,SRAM with a capacity of 512x32 is designed and passed the post-simulation verification.The post-simulation results show that: under 0.6V and 0.9V operating voltages,the overall readout delay of the proposed SRAM is 2.12 ns and 430 ps,respectively.Compared with the traditional SRAM,the readout delay of the proposed SRAM is reduced by 42% and 25% at 0.6V and 0.9V operating voltages,respectively.Under 0.6V and 0.9V operating voltages,the read power of the proposed SRAM is 1.62 p J and3.45 p J,respectively.Compared with the traditional SRAM,the read power of the proposed SRAM is reduced by 17% and 13% at 0.6V and 0.9V operating voltages,respectively.