10bit 1MS/s Ultra-Low Power SAR ADC Design

With the rapid development of today's society,people pay more attention to their own physical health and quality of life.A large number of smart wearable devices and biomedical detection devices have been created.These wearable devices are small and convenient,and contain a variety of sensor chips to detect them all the time.In view of the various physiological indicators of the human body,due to the particularity of its application scenario,it requires higher battery life than other electronic devices,and the development of battery technology is still in the bottleneck period.In order to solve this problem,researchers will Looking at the low-power design of products,the analog-todigital converter(ADC)is the core of this type of sensor,and it is particularly necessary to reduce its power consumption.Because this type of bioelectric signal has the characteristics of low speed,medium accuracy,and strict requirements on power consumption,compared with other types of ADCs,the successive approximation analog-to-digital converter(SAR ADC)has a simple structure,a small area,and a high power consumption.It is widely used due to its extremely low power consumption.This article designs an ultra-low-power SAR ADC based on the SMIC 55 nm CMOS process,and proposes a new gate voltage bootstrap switch based on the transmission gate,which effectively improves the linearity and harmonic distortion of the sampling switch.At the same time,it is modeled by Matlab.The tri-level capacitive digital-to-analog converter(CDAC)algorithm is optimized,and a high-capacity isolation technology is proposed.In combination with the improved CDAC scheme,the frequency of the highest-capacitance flip-flop during conversion is reduced.A 99.5% reduction in energy.The sampling circuit was adjusted for the non-linearity introduced by the high-position isolation switch,and the original transmission gate was replaced by a gate voltage bootstrap switch,which speeded up the DAC settling time and improved the linearity of the overall design.The comparator is latched,and the structure and parameters are adjusted and optimized for problems such as offset and kickback noise;the control logic adopts asynchronous control,and the three-input AND gate is added to form the D flip-flop to self-lock.Only one D flip-flop is inverted,which reduces the power consumption of the register bank.Finally,the overall circuit was simulated in Cadence's spectre.At a sampling rate of 1MSps and an input frequency of 16.601 KHz,the SNDR is approximately 60.3d B and the SFDR is approximately73.6d B.The ENOB of the designed SAR ADC is 9.81 bits,With a 1.1V power supply,the total power consumption is 954 n W,which reduces the FOM value of the designed SAR ADC to 1.041 fJ/ conversion-step.