A Study Of 10-bit Asynchronous High-speed SAR ADC

With the arrival of the intelligent era,a variety of portable electronic equipment has processed into a rapid development period,and intelligent electronic equipment has penetrated into all aspects of life,especially in bio-medical,wireless transmission,smart home and 4G communications.With the development of CMOS technology and the improvement of the demand for electronic equipment,the system integration and operation speed of the circuit need to be improved,and the power consumption need to be reduced.In nature,sound,temperature and light all are analog signals.For achieving subsequent processing,Analog-to-digital converter(ADC)is used to convert the analog signal which is continuous in time and amplitude to the digital signal which is dispersed in time,and quantified in amplitude.The performance of ADC gradually becomes the bottleneck of high resolution,high speed and low power circuit system.Especially in recent years,innovation in wireless communications and consumer electronics drive ADC performance to be improved.In order to meet the rapid transmission of a large number of video and audio signals,research on high speed,high resolution and low power SAR ADC has become a hot research topic.Based on the detailed analysis of the working principle and circuit structure of SAR ADC,specific circuit modules are optimized and a 10 bit 50MPS high speed SAR ADC is proposed and designed in this paper.A differential structure is used into the SAR ADC to suppress common mode noise and improve the linearity.By using the asynchronous sequential logic,the SAR ADC can effectively use the conversion time to reduce overall power consumption and to improve the speed.In order to reduce the influence of the charge leak error,a dynamic latch unit is added into the logic circuit.As the charging time is too long for the bootstrap capacitor in the traditional bootstrapped switch,an additional n-MOSFET is introduceded to increase the sampling speed by quickly adding the voltage at the control of the clock.Simultaneously,a two-stage dynamic comparator is used to improve the speed and reduce the static power consumption of the chip.Through the study of the existing sequence circuit,a new switching scheme is proposed and designed,which uses the bottom plate sampling as the sample mode.The newly sample mode not only effectively reduces the capacitor area,but also reduces the settling time of DAC.Further design optimization reduces the invalid voltage switching and reduces the power consumption of DAC capacitor array.Compared with the traditional scheme,the proposed switching scheme has higher efficiency of power and the capacitor area,the power and the capacitor area of which are decreased by 98.73%and 75%,respectively.In the layout design,the comparator and the SAR logic module should be isolated,and the isolation ring is added to reduce the crosstalk and to improve the anti-interference ability of the system.The capacitor array is symmetrically arranged and uses centrosymmetric structure.The dummy capacitor is added to increase the capacitance matching.The proposed ADC is implanted in the SMIC 65nm technology.The simulated results show that at 1.2V supply voltage and 50M sampling rate,it achieves SNR of 59.81dB,SNDR of 59.6dB,ENOB of 9.6bit,SFDR of 78.46dB,THD of-72.95dB.The FOM of the designed chip is 5.3fJ/conversion-step,and the total area is 320×700?m~2.